Overlay, Critical Dimension, And Z-Height Metrology Solutions For Advanced Packaging

The consumer’s thirst for AI-based applications is powering the ever-evolving electronics industry. Applications delivering higher levels of information in human language-like form, smarter at-home gadgets, the ability to receive a medical diagnosis without a doctor’s visit and the convenience of autonomous vehicles are among the applications powering this thirst. To better enable these applications and further extend the promise of Moore’s Law, semiconductor designers and manufacturers continue to explore innovative ways to deliver more functionality in increasingly smaller packages. Heterogeneous integration via 2.5D and 3D technologies are growing in support of this effort.

Fig. 1: Technology & Market Trends for Advanced Packaging | SSI 2023 | Yole Group

At present, two-dimensional (2D) scaling is running up against physical limitations. However, stacking chips vertically offers manufacturers a solution to achieve higher levels of functionality per unit area.

Three-dimensional (3D) heterogeneous integration enables semiconductor designers and manufacturers to combine multiple technologies, processes and functionalities in a single package. Not only does this advanced packaging innovation extend Moore’s Law, 3D heterogeneous integration delivers more capability with lowered power consumption.

Fig. 2: A typical AI package.

To create these 3D devices, advanced packaging manufacturers take known good die with varying functions, mix, match, vertically stack and connect them via through silicon vias (TSVs) and micro bumps. The final integrated package is manufactured from individual die, a.k.a. chiplets, offering specific work functions with each delivering leading edge capability. In this case, heterogeneous integration results in a more powerful package delivering a wider array of capabilities. This requires the integration process to be executed according to very exact requirements. Any slight variation in process uniformity can result in unacceptable performance variations, lower yield and profit loss.

High bandwidth memory (HBM) is a classic example in advanced packaging where precise metrology is essential to delivering more functionality per unit area, i.e., higher input/output densities per unit area. Enabling this are TSVs, Cu pillars, micro bumps and redistribution layers (RDLs) used on the frontside and backside of the wafers to facilitate vertical connections between the stacked die. The formation of the microbumps involves the deposition of underlying metals, lithography and etch steps to form a window/opening for the Cu pillar.

Inadequate control of step height for pillars and microbumps can result in poor signal integrity, while failures to meet CD requirements impact signal integrity and increase power consumption and result in poor thermal performance. After the formation of the microbumps, a redistribution layer (RDL) is added to facilitate die-to-die electrical connection. Failure to meet the RDL width or RDL pad diameter degrades signal performance, leading to poor reliability and yield loss. Additionally, on product overlay (OPO) during the pillar formation process is key in achieving device parametrics.

Next-generation processes utilize 18μm pitches, 9μm diameters and total on-pillar bump heights of approximately 17μm. On a 300mm wafer, this yields about 200 million bumps. The viability of microbumps is expected to end at the 10μm pitch. At this level of pitch, there would be about 500 million bumps on a 300mm wafer.

Smartly designed metrology solutions delivering precise measurements enable manufacturers to maintain yield and productivity of high-volume manufacturing (HVM) packaging lines. Optimally, a single solution with the capability to measure overlay, CD and step height allows engineers to maximize their total cost of ownership.

The ability to control for these three use cases (overlay, CD and step height) with such a tool is facilitated by employing a microscope designed to mitigate performance-compromising signal to noise ratios and unique hardware to facilitate benchmark levels of multi-plane focus control, while offering Z-stage-providing nanometer-level vertical resolution and AI driven software and analytics enhancing time to solution and the meaningful disposition of work in progress.

In conclusion, high performance computing and AI applications are driving the demand for increased functionality and higher performance, while vertical integration via HBM, 2.5D and 3DIC technologies strives to keep pace. These technologies have demanding performance requirements, resulting in increasing numbers of I/O counts and RDL line/space and CDs shrinking below 5µm. A single precision metrology tool is optimal to deliver the overlay and dimensional process control manufacturers need to maintain yield and manage cost.