tag: Cadence

Cloud Drives Changes In Network Chip Architectures
By Ann Mutschler - 03 Oct, 2018 - Comments: 0

Cloud data centers have changed the networking topology and how data moves throughout a large data center, prompting significant changes in the architecture of the chips used to route that data and raising a whole new set of design challenges. Cloud computing has emerged as the fast growing segment of the data center market. In fact, it is expected to grow three-fold in the next few years, a... » read more

Blog Review: Oct. 3
By Jesse Allen - 03 Oct, 2018 - Comments: 0

Applied's Buvna Ayyagari-Sangamalli notes that the requirements of AI are challenging the entire design ecosystem, and while new materials are necessary, so is keeping up the current pace of architecture and EDA development. Mentor's Joe Hupcey III digs into how to handle counters effectively with formal by reducing their size or replacing them with abstract models to allow formal engines to... » read more

RISC-V Inches Toward The Center
By Ann Mutschler - 01 Oct, 2018 - Comments: 1

RISC-V is pushing further into the mainstream, showing up across a wide swath of designs and garnering support from a long and still-growing list of chipmakers, tools vendors, universities and foundries. In most cases it is being used as a complementary processor than a replacement for something else, but that could change in the future. What makes RISC-V particularly attractive to chipmaker... » read more

Is Cloud Computing Suitable for Chip Design?
By Brian Bailey - 27 Sep, 2018 - Comments: 2

Is semiconductor design being left behind in a cloud-dominated world? Finance, CRM, office applications and many other sectors have made the switch to a cloud-based computing environment, but the EDA industry and its users have hardly started the migration. Are EDA needs and concerns that different from everyone else? We are starting to see announcements from EDA companies, but few cheerleaders... » read more

The Revenge Of The Digital Twins
By Frank Schirrmeister - 27 Sep, 2018 - Comments: 0

How do we verify artificial intelligence? Even before “smart digital twins” get as advanced as shown in science fiction shows, making sure they are “on our side” and don’t “go rogue” will become a true verification problem. There are some immediate tasks the industry is working on—like functional safety and security—but new verification challenges loom on the horizon. As in pr... » read more

Domain Crossing Nightmares
By Brian Bailey - 27 Sep, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Analog Reliability Analysis for Mission-Critical Applications
By Cadence - 26 Sep, 2018 - Comments: 0

Rapidly increasing electrical content in automobiles is driving the need for revolution in analog integrated circuit (IC) design methodology. Compared to designing for consumer electronics, designing for mission-critical applications—industrial, medical, space, and automotive—requires a different approach to reliability analysis. We will explore how reliability analysis needs to change for ... » read more

Blog Review: Sept. 26
By Jesse Allen - 26 Sep, 2018 - Comments: 0

VLSI Research's Dan Hutcheson chats with GlobalFoundries CEO Tom Caulfield about the company's changing strategy, how the company got to its present point, and how many companies will be using leading edge technologies. Synopsys' Taylor Armerding looks for what's changed (or not) for the state of software security and breach disclosure regulations in the year since the massive Equifax data b... » read more

Week In Review: Design, Low Power
By Jesse Allen - 21 Sep, 2018 - Comments: 0

Tools & IP Cadence unveiled deep neural-network accelerator (DNA) AI processor IP, Tensilica DNA 100, targeted at on-device neural network inference applications. The processor is scalable from 0.5 TMAC (Tera multiply-accumulate) to 12 TMACs, or 100s of TMACs with multiple processors stacked, and the company claims it delivers up to 4.7X better performance and up to 2.3X more performance p... » read more

Blog Review: Sept. 19
By Jesse Allen - 19 Sep, 2018 - Comments: 0

Applied Materials' David Thompson shares the new DARPA program that is focused on using correlated electrons to develop a new type of switch with quantum effects, potentially leading to unprecedented switching speeds. Mentor's Joe Hupcey III argues that for the most effective formal analysis, assertions should be as simple as possible and shares some tips on decomposing big assertions. Ca... » read more

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