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Physical Verification For Photonics Integrated Circuits

While promising for a range of networking applications, photonic ICs present a unique set of verification challenges.

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Silicon photonics is a promising solution for the explosive growth of data volume and network traffic in computing and communications. Silicon photonics integrates photonics applications on a silicon wafer, utilizing mainstream Si-based technology. Photonics integrated circuits (PIC) offer several advantages over traditional integrated circuits: faster data transfer speeds, lower power consumption and smaller footprint. Cloud data centers, automotive lidar and mobile/wearable devices are some of the key drivers for the recent silicon photonics market growth.

Photonics IC designs present a unique set of challenges for physical verification in the design flow. PIC design layout contains components that require smooth curves to operate efficiently, unlike traditional IC designs that use Manhattan and 450 geometries. Photonics circuits need curvilinear shapes and special bends to confine, steer and guide light. As a result, PIC designs employ a variety of curvilinear structures such as wave guides, Euler bends, ring filters etc. Verifying such non-Manhattan layouts with traditional DRC methods results in a huge number of false errors that are impossible to debug.

EDA tools translate ideal curvilinear shapes into discretized polygons on the GDS grid, which can result in inaccurate approximations. To get more accurate DRC results, runsets should be enhanced with PIC design specific rule definitions for correct treatment of curvilinear layout geometries. For example, tolerance factor controls detect curved segments of the geometry and eliminate false errors during non-45 edge checks (figure 1).


Figure 1: Non-45 degree shapes

Finer resolution settings help to capture true error regions that may otherwise be missed during minimum space checking (figure 2). Accurate DRC checking for PIC design’s non-traditional layouts require special considerations for rules such as angle check, min/max area, min/max distance, min/max space, enclosure, min/max width and partial overlap.


Figure 2: Minimum space check – example

Furthermore, intelligible methodology and good debugging flows are essential to contain a multitude of false violations. For instance, spacing check on a long curvilinear shape may report several shorter error shapes for a single violation. Defining appropriate connectivity settings in the runset will produce one single continuous error shape and avoid unnecessary complexity during debugging. Designers can also employ built-in waiver methodologies to exclude select waived rules and irrelevant checks. PIC designs can have some valid structures (e.g. light coupler) that violate a pre-defined rule in the runset. Such structures can be marked in the layout to be excluded from checking and thus eliminate redundant debugging.

In conclusion, clean and comprehensive physical verification of photonics IC designs is possible today. Established tools such as IC Validator can reliably verify the unique layout and design styles of silicon photonics designs and have been used in design tapeouts to greatly reduce design time and improve tape-out confidence.

For more information about IC Validator, click here.



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