Physical Verification For Silicon Photonics: Don’t Panic!

Silicon photonics augments traditional electrical signals in integrated circuits (ICs) with light transmission to speed up data transfer and reduce power consumption. According to MarketsandMarkets, the overall silicon photonics market is worth approximately $774.1M in 2018, and is expected to reach $1,988.2M by 2023, at a CAGR of 20.8% between 2018 and 2023  [1]. Cloud computing is one market driving an exponential increase in data traffic, along with telecommunications, military, defense, and aerospace. Rising demand for high bandwidth and high data transfer capabilities in data centers and high-performance computing, coupled with the need for reduction in power consumption, are the key factors driving growth across the silicon photonics market.

However, this growing demand for photonics ICs (PICs) also increases the need for a solid, stable physical verification platform for PIC designs. The disparity between traditional electronic IC (EIC) design and manufacturing, with its long-established and proven verification processes and tools, and the new PIC designs, which introduce novel and challenging verification requirements, opens up opportunities for electronic design automation (EDA) companies to provide new and innovative solutions. Using existing tools in new ways, they are creating verification flows that can assess the electrical and optical behavior of PICs, similar to existing verification flows for EICs.

Silicon photonics design
PIC designs differ from EIC designs in one very critical element—the geometrical construction of basic components. EICs use a Manhattan geometry; circuits are designed on a rectangular grid that only allows for 0°, 45°, and 90° angles. In contrast, PIC designs include a wide variety of curvilinear structures, such as delay lines, ring resonators, waveguides, grating couplers, etc. (Figure 1).

Figure 1. Common PIC components. (Sources: IMEC and IHP. Used by permission.)

In addition, PIC designs do not use traditional design schematics, which makes the concept of classic layout vs. schematic (LVS) verification a foreign notion to photonics designers. However, they must still be able to ensure that photonics circuit ports are properly connected to electronic circuit nodes, and to enable device and device parameter recognition.

PIC physical verification challenges
Designers measure the geometrical integrity of an EIC design with design rule checking (DRC), which determines if the design’s physical layout complies with the manufacturing requirements (design rules) set by the foundry. Because traditional EIC designs consist of Manhattan shapes placed on a rectangular grid, the measurement of various geometrical parameters is fairly straightforward, and accuracy can be quite precise.

In PICs, placing curvilinear structures on a rectangular grid presents a challenge for existing IC verification tools and processes (Figure 2). Precise measurement is problematic due to edge and vertex “snapping,” which occurs when the vertices of the curved shapes must adapt to the precision of linear mapping, resulting in an imprecise approximation.

Figure 2: Physical verification challenges of curvilinear structures.

To obtain more accurate results, this effect must be compensated for during the geometrical parameter measurements. Extraction and validation of these non-traditional shapes requires new parameters, such as bend curvature and curvilinear path length. Reconstructing or reinventing an entire PIC toolset and verification flow to fit such structures is unrealistic, given the time and resources that would be required. Alternatively, the EDA industry has developed new PIC verification techniques that can achieve the required degree of accuracy with modest modifications to existing EIC toolsets.

A useful addition to the PIC verification toolset is equation-based DRC, which can apply complex conditional DRC with multi-dimensional tolerance values in place of traditional DRC arithmetic calculations. Without the use of equation-based DRC, PIC physical verification generates many false errors, due primarily to edge snapping or rounding errors during measurements (Figure 3).

Figure 3: Using traditional DRC over curvilinear structures creates many false errors [2].

To filter out these false violations, designers add equation- based DRC to traditional DRC checks to detect the curved segments of the design and apply the necessary tolerance factors to eliminate the false errors. The introduction of equation-based filtering and checking enables a whole new range of DRC capabilities for silicon photonics, where multi-dimensional equations can be evaluated to accurately check the geometric validity of photonics designs (Figure 4).

Figure 4: Using equation-based functionality over curvilinear structures reduces false violations [2].

However, as the maximum edge length gets smaller, more edges are needed to represent a single polygon. Because DRC verification tools are edge-based, as the number of edges increases, tool runtime also increases. Designers must manage the conflict of using a large number of edges to accurately represent PIC components vs. the possible runtime impact. To perform proper DRC for PIC layouts more efficiently, many PIC designers have adopted a new coding style, in which the maximum edge length plays a significant role in performance tunability vs. results accuracy.

In some physical verification tools, equation-based DRC runtime may not incur any significant impacts, due to multiple runtime optimization strategies built into the tool. However, runtime impact should always be considered when developing DRC process design kits (PDKs) for silicon photonics.

PIC circuit verification challenges
Another challenge in building a PIC design flow is the absence of a SPICE source netlist. EIC schematic capture and simulation (design, automated layout, LVS, parasitic extraction [PEX], re-simulation, etc.) is heavily dependent upon SPICE circuit simulation, but there is no generically-equivalent PIC simulation approach. TCAD-like tools are typically used for accuracy, but are capacity/performance limited, due to the lack of a common format for verification and validation across the flow.

The waveguides in PICs act as an optical interconnect between various circuit components, but are also the building blocks of most PIC devices. Unlike interconnect in EICs, waveguides must be treated as devices instead of as ideal interconnect, due to the difference in the concept of connectivity in photonics. The parameters of a waveguide play a pivotal role in its operation, owing to their impact on the modes propagating the waveguides. Also, simple electronic concepts such as shorts and opens are different in photonics design. For example, two waveguides might overlap, creating a four-port network, without resulting in a shorted interconnect (Figure 5).

Figure 5: Extraction of PIC device parameters in LVS.

Comparing a classic electronic LVS flow to photonics LVS requirements can help determine the missing LVS components—which are optical connectivity and the validation of curved design shapes (Table 1). Optical connectivity and photonic device functionality are validated through parameter extraction and comparison: width, curvilinear path length, and bend curvature, with the limitation being that we must assume a curve type for said curve (e.g., circular arc, Bessier, adiabatic, etc.).

Traditional LVS extracts the assumed curvature and matches it to a source. Shape-matching LVS, a new method of validating curvilinear design, starts with the source and validates curvature (Figure 6). Table 2 describes the difference in parameter extraction between traditional LVS and shape-matching LVS.

Figure 6: Shape-matching LVS.

Multiple options exist for methods used to match device shapes:

• Re-instantiation of Pcell, where Pcell is overlaid to the intended location and XORed, which will find differences/error due to
• Pattern matching, which is easy to implement, but requires at least some Manhattan edges for matching. There is also a need to determine allowed tolerances and how to extract parameters based off these

A comparison between classic LVS, enhanced LVS, and shape-matching LVS in Figure 7 shows the superior coverage of shape-matching LVS.

Figure 7: Comparison between various LVS techniques for silicon photonics.

Litho-friendly design simulation
Historically, IC design processes, particularly at older nodes, assume that what is drawn is what will be delivered (mask to silicon). At advanced nodes, to compensate for the finite size of the lens (which does not capture all the mask diffraction order), lithography techniques such as optical proximity correction (OPC) must be used to modify the layout before manufacturing to ensure it will comply with the original drawn intent.

For PICs, it is crucial that designers properly and accurately model the final shapes of the circuit, due to the direct impact on circuit performance. For multi-project wafer (MPW) runs, designers typically require multiple iterations of physical device manufacturing to understand and improve the circuit behavior (Figure 8). However, physical iteration is very time-consuming and extremely expensive.

Figure 8: Fabricated Bragg waveguide bandwidth is smaller than design intent bandwidth (courtesy of Xu Wang [3]).

Alternatively, designers can take advantage of litho-friendly process design kits (PDKs) supplied by the foundry. Foundry lithographers and technology access groups (TAGs) use litho-friendly design (LFD) tools from EDA companies to develop these PDKs. Using an LFD tool in conjunction with an LFD PDK enables designers to perform a variety of process simulation checks previously only available to lithographers working in semiconductor foundries. These checks can identify potential lithographic resolution issues prior to tapeout (Figure 9). Design teams can then apply the necessary design modifications or OPC techniques to ensure manufacturability and performance. With access to an automated virtual lithographic process, designers can shave months from their schedules while avoiding spending money on silicon that does not meet design intent.

Figure 9: Typical LFD workflow.

Conclusion
The growing market for silicon photonics circuits has led to the need for reliable, automated physical verification and manufacturing verification process flows that address the unique physical characteristics of silicon photonics designs. Fortunately, there is no need to reinvent the tools and processes already in place for electronic IC verification. Expanding the use of established functionality like equation-based DRC, shape-matching LVS and litho-friendly design enables designers to accommodate the new components and design concepts of silicon photonics designs.

References
[1]  MarketsandMarkets, “Silicon Photonics Market by Product (Transceiver, Switch, Variable Optical Attenuator, Cable, Sensor), Application (Data Center, Telecommunications, Military & Defense, Medical and Life Sciences, Sensing), Component, and Geography – Global Forecast to 2023” February 2018.
https://www.marketsandmarkets.com/Market-Reports/silicon-photonics-116.html

[2]  R. Cao, J. Ferguson, F. Gays, Y. Drissi, A. Arriordaz and I. O’Connor, “Silicon photonics design rule checking: Application of a programmable modeling engine for non-Manhattan geometry verification,” 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC), Playa del Carmen, 2014, pp. 1-6. doi: 10.1109/VLSI-SoC.2014.7004173
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7004173&isnumber=70041501

[3]  X. Wang et al., “Lithography simulation for the fabrication of silicon photonic devices with deep-ultraviolet lithography,” The 9th International Conference on Group IV Photonics (GFP), San Diego, CA, 2012, pp. 288-290. doi: 10.1109/GROUP4.2012.6324162
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6324162&isnumber=6324060