Existing methods for considering power supply variation and noise are grossly inadequate.
The convergence of advance process technology, increasing levels of integration, and higher operating frequencies pose considerable challenge to IP designers whose circuits are required to function in variety of conditions. Full-custom and mixed signal circuit designers ensure that their circuits will function by simulating for various operating conditions (PVT, input stimuli, etc). One key aspect for the reliable operation of these complex circuits is the quality of the voltage supply they receive. However, it is becoming increasingly apparent that traditional and existing methods of considering power supply variation and noise is grossly inadequate and do not consider the multiple factors that contribute to power and ground supply noise. Also existing methods do not provide sufficient capabilities to predict the impact of the fluctuation in the power and ground supplies on various key circuit parameters like noise margin, clock jitter, and delays. Additionally, in traditional IC design methodologies, the custom IPs are typically designed and verified independent of the environment they operate in. However, the impact of integrating digital and mixed- signal IP blocks in SoCs and ASICs is considerable and is manifested in both directions – from the IP to the chip and from the chip to the IP.
The critical area of power noise analysis and reliability verification targeting analog and mixed signal circuits, both by themselves and in context of the chips they operate in, have not been adequately addressed by existing solutions. There is a clear and present need for an integrated analysis, verification and optimization solution. To read more, click here.
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