Power Just One Piece Of The Puzzle At 10nm And Below

With dynamic power density and rising leakage power becoming more problematic at each new node, it is more important than ever to look at designs today with power in mind from the very start.

As part of this complex picture of electronic design today, every piece in the design flow must tie together for the greatest efficiency and optimization.

While this is partly power, there are more pieces to this puzzle.

Especially considering with the advent of advanced process nodes — 10nm, 7nm and below — IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs, observed Sudhakar Jilla, group director of marketing for the IC implementation division at Mentor, a Siemens business.

Yet at the same time, they also face a slew of new design challenges with every new node transition that severely impacts design performance, power, and time-to-market requirements, he said. “While feature sizes keep shrinking, lithography still uses 193 nm wavelength light, which makes printability and manufacturability more challenging due to increased distortion. This drives the need for multi-patterning during manufacturing and significant layout restrictions during design implementation.”

Some of the technological developments currently contributing to the emergence of progressively more diverse and complex design and manufacturing constraints include generic shrinking of geometries—both library cells and wires; double patterning (starting from 20nm), which makes pin access and routing on lower layers more difficult; the introduction of FinFET, which changes the layout structure of standard cells and further shrunk library cell dimensions beyond normal scaling; and divergence at 10nm such as self-aligned double patterning vs. more traditional multi-patterned litho-etch, each presenting unique challenges to place and route.

At the same time, the introduction of multi patterning and FinFET (3D) transistors to realize lower power and higher performance has only added to the design complexity and imposes more restrictions on the implementation flow, noted Arvind Narayanan, a product marketing architect at Mentor. Because of this, physical implementation tools for advanced node designs not only need to address the traditional challenges of large design sizes, stringent low-power requirements, high frequency targets and process variations, but also handle the complexities of multi-patterning and FinFETs throughout the design flow.

Other considerations for design at 10nm, 7nm and below include:

— Multi-patterning and FinFETs impact all the key engines in the physical implementation flow including placement, routing, floorplaning, timing and extraction. The complexity and number of DRC rules along with the multi-patterning rules has increased significantly and poses a big challenge to the router. Tighter design rules and FinFET process requirements, such as voltage threshold-aware spacing, implant layer rules, etc., impose restrictions on placement, floorplanning, and optimization engines that directly impacts design utilization and area. Multi-patterning closure and timing closure are inter-dependent, each requiring minimal design perturbations and can increase design closure time. In order to account for multi-patterning and FinFETs, the entire place and route flow must be completely revamped.

— Design implementation tools have been completely revamped to provide a comprehensive multi-patterning aware flow to address the challenges of smaller nodes. They address all the routing rules required for 10/7nm and below, including dealing with the interactions between multi-patterning and FinFETs. The database has been architected to handle the requirements for multiple masks and to support anchoring and propagation of pre-colored objects. All the key engines in the entire flow, including placement, optimization, timing, and extraction are FinFET and multi-patterning aware.

— Due to the stringent multi-patterning and FinFET rules and constraints, design utilization/area has become a big challenge that needs new solutions. The design tools enable concurrent optimization and fixing for timing, signal integrity, power, and multi-patterning for the fastest time-to-results. The optimization engines performs dynamic density recovery, area management, and white space optimization throughout the flow for the best design utilization. The global-router based congestion modeling is utilized by the optimization engine and the router to accurately model congestion and pin density. To address signal integrity and multi-patterning closure, techniques such as buffering and sizing concurrently consider multiple cost functions.

— Although the total power use of FinFETs are lower than that of planar CMOS transistors, the dynamic power component is higher in proportion to the leakage power. To minimize dynamic power, optimization capabilities including activity-driven placement, pin swapping, register clumping, remapping, and power-aware clock tree synthesis are employed.

What this comes down to is that as design complexity continues to grow and designs migrate to smaller nodes, designers face significant challenges due to multi-patterning, FinFETs, complex DRC/DFM, increased design sizes, and multiple design goals. Fortunately, the next generation physical design implementation tools provide a path forward to take power, performance, and area into account concurrently, and from the outset of design.