Power/Performance Bits: Aug. 9

Capacitors in interposers
Scientists at Tokyo Institute of Technology developed a 3D functional interposer containing an embedded capacitor. They tout the design as saving package area and reducing wiring length, resulting in less noise and power consumption.

The capacitive elements are embedded inside a 300mm silicon piece using permanent adhesive and mold resin. The interconnects between the chip and the capacitor are made directly with through-silicon vias and without the need for solder bumps. “Our bumpless 3D functional interposer enables a notable reduction in package area of about 50% and an interconnect length a hundred times shorter,” said Takayuki Ohba, a professor at Tokyo Tech.

Their fabrication method also avoided warping in the wafer due to the resin and misplacement errors due to void pockets in the adhesive, two common problems of bumpless chip-on-wafer designs.

In testing and theoretical calculations, they estimate the functional interposer reduces wiring resistance by about a hundred times and had lower parasitic capacitance compared to conventional designs, which could allow for lower supply voltages to be used.

“The chip-on-wafer integration technology we are developing will open up new routes in the evolution of semiconductor package structures,” added Ohba.

2D boron nitride for electromigration
Researchers from the University of South Florida and Japan’s National Institute for Materials Science propose a new way to mitigate electromigration in electronic interconnects. The method coats copper metal interconnects with hexagonal boron nitride (hBN), an atomically-thin insulating 2D material.

“This work introduces new opportunities for research into the interfacial interactions between metals and ångström-scale 2D materials. Improving electronic and semiconductor device performance is just one result of this research. The findings from this study opens up new possibilities that can help advance future manufacturing of semiconductors and integrated circuits,” said Michael Cai Wang, an assistant professor of mechanical engineering at USF. “Our novel encapsulation strategy using single-layer hBN as the barrier material enables further scaling of device density and the progression of Moore’s Law.”

The researchers were able to passivate copper interconnects with a monolayer hBN using a back-end-of-line (BEOL) compatible approach. These interconnects demonstrated more than 2500% longer device lifetime and more than 20% higher current density than otherwise identical control devices. And since hBN is ångström-thin, the process would allow denser ICs compared to those with conventional barrier materials.

Wang noted that the process may have applications beyond semiconductors. “Our findings are not limited only to electrical interconnects in semiconductor research. The fact that we were able to achieve such a drastic interconnect device improvement implies that 2D materials can also be applied to a variety of other scenarios.”

The team is working on ways to speed up the process for use in commercial fabs.