Power/Performance Bits: Feb. 18

Cryogenic memory
Researchers at Oak Ridge National Laboratory demonstrated a new cryogenic memory cell circuit design based on coupled arrays of Josephson junctions. Such a memory could help enable exascale and quantum computing.

The cells are designed to operate in super cold temperatures and were tested at just 4 Kelvin above absolute zero, about minus 452 degrees Fahrenheit. At these cold conditions, atoms slow and some materials become superconductors, with no electrical resistance and little energy lost as heat.

“In our design, we have attempted a fundamentally different path that employs small, inductively coupled arrays of Josephson junctions,” said Yehuda Braiman of ORNL’s Computational Sciences and Engineering Division. “If scaled, such memory cell arrays could be orders of magnitude faster than existing memories while consuming very little power.”

Josephson junctions are cryogenic electrical devices that can harness magnetic flux to store data.

The design, which uses three inductively coupled Josephson junctions, allows all of the basic memory operations — read, write and reset — to be implemented on the same three-Josephson-junction cell. This capability may help add stability while saving space and energy as the cell circuits are scaled into larger arrays, a step that has caused problems for existing technologies.

“People are looking for something different,” Braiman said. “We are using typical junctions, which do not require any particular fabrication design. It’s an inherently different principle itself that makes the cell operate.”

SeeQC, a superconducting technology company, helped test the cell circuits. SeeQC scientists fabricated the ORNL design onto 5 millimeter by 5 millimeter chips with circuits at each corner. The chips were mounted onto a long pole, called a cryogenic probe, connected by wires to a desktop computer at room temperature. Scientists dunked the chips into a specialized container filled with liquid helium to cool the circuit to a temperature of 4 Kelvin. They then sent electrical pulses from the room temperature computer to test the memory function of the cells.

Tests of four cell circuit designs with slightly different specifications demonstrated not only that the cells work, but also that they function robustly and operate in a wider range of experimental parameters than the team had initially envisioned.

There is still more work to be done. “What has been demonstrated is on a single cell level,” said Braiman. “What people care about are very large arrays of memory cells.” As a next step, the team will work to implement their cells in increasingly large arrays and test designs using recently purchased cryogenic testing equipment.

3D inductor
Researchers at the University of Illinois, Stanford University, and Hefei University of Technology developed a 3D inductor that can be manufactured in a standard 2D process while taking up much less chip space. The microchip inductor uses fully integrated, self-rolling magnetic nanoparticle-filled tubes and is capable of tens of millitesla-level magnetic induction.

Compared to the 2D spirals of wire that make up traditional microchip inductors, the team’s design is comprised of a rolled membrane which allows for wire spiraling out of plane and is separated by an insulating thin film from turn to turn.

Previous wire membranes developed by the researchers were 1 millimeter long when unrolled but took up 100 times less space than the traditional 2D inductors. The new wire membranes are 10 times the length at 1 centimeter, allowing for even more turns – and higher inductance – while taking up about the same amount of chip space.

A scanning electron microscope micrograph of a rolled microinductor architecture, approximatley 80 micrometers in diameter and viewed from one end looking inward. (Reprinted with permission from X. Li et al., Science Advances (2020). Courtesy Xiuling Li / Univesrity of Illinois)

“A longer membrane means more unruly rolling if not controlled,” said Xiuling Li, an electrical and computer engineering professor at the University of Illinois and interim director of the Holonyak Micro and Nanotechnology Laboratory. “Previously, the self-rolling process was triggered and took place in a liquid solution. However, we found that while working with longer membranes, allowing the process to occur in a vapor phase gave us much better control to form tighter, more even rolls.”

Additionally, the researchers added a solid iron core to the new inductor by filling already-rolled membranes with an iron oxide nanoparticle solution. “The most efficient inductors are typically an iron core wrapped with metal wire, which works well in electronic circuits where size is not as important of a consideration,” Li said. “But that does not work at the microchip level, nor is it conducive to the self-rolling process, so we needed to find a different way.”

“We take advantage of capillary pressure, which sucks droplets of the solution into the cores,” Li said. “The solution dries, leaving iron deposited inside the tube. This adds properties that are favorable compared to industry-standard solid cores, allowing these devices to operate at higher frequency with less performance loss.”

Li noted that one of the major challenges remaining is heat dissipation. “We are addressing this by working with collaborators to find materials that are better at dissipating the heat generated during induction. If properly addressed, the magnetic induction of these devices could be as large as hundreds to thousands of millitesla, making them useful in a wide range of applications including power electronics, magnetic resonance imaging and communications.”

Reducing IoT lag
Researchers at the University of Pittsburgh propose a method to improve network congestion and reduce lag caused by a large number of IoT devices with a system that would use currently underutilized resources in an existing wireless channel to create extra opportunities for lag-free connections.

The process wouldn’t require additional hardware or wireless spectrum and targets networks with many wireless connections, like factories and warehouses.

“The network’s automatic response to channel quality, or the signal-to-noise ratio (SNR), is almost always a step or two behind,” said Wei Gao, associate professor in the Department of Electrical and Computer Engineering at the University of Pittsburgh. “When there is heavy traffic on a channel, the network changes to accommodate it. Similarly, when there is lighter traffic, the network meets it, but these adaptations don’t happen instantaneously. We used that lag – the space between the channel condition change and the network adjustment – to build a side channel solely for IoT devices where there is no competition and no delay.”

This method, which the authors call “EasyPass,” would exploit the existing SNR margin, using it as a dedicated side channel for IoT devices. Lab tests have demonstrated a 90 percent reduction in data transmission delay in congested IoT networks, with a throughput up to 2.5 Mbps over a narrowband wireless link that can be accessed by more than 100 IoT devices at once.

“The IoT has an important future in smart buildings, transportation systems, smart manufacturing, cyber-physical health systems, and beyond,” said Gao. “Our research could remove a very important barrier holding it back.”