Process Modeling Exploration for 8 nm Half-Pitch Interconnects

Understand the effects of eSADP, eSAQP and iSAOP patterning options in fabricating an 8nm half-pitch interconnects.


In this paper, we simulate eSADP, eSAQP and iSAOP patterning options to enable fabrication of 8 nm Half-Pitch (HP) interconnects. We investigate the impact of process variations and patterning sensitivities on pitch walking and resistance performance. The overall yield is also calculated for eight line CDs as well as M2-via-M1 via segment resistance and compared for all options. Process sensitivity simulation results enable us to evaluate the most robust options for 8 nm HP patterning.

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