How to manage hotspots at 7/5nm and beyond.
With the continued need for shrinking pattern dimensions, semiconductor manufacturers continue to implement more complex patterning techniques, such as advanced multi-patterning, for the 10nm design node and beyond. They also are investing significant development effort in readying EUV lithography for production at the 7/5nm design nodes. Additionally, semiconductor manufacturers’ use of design technology co-optimization is driving investigation of new design layouts and integration schemes to further enable smaller design nodes. With these industry developments come challenges, including the proliferation of hotspots – design- or process- related systematic defects at critical die locations – and the relation between hotspots and increasingly narrow process margins. These challenges drive a need for technologies to accurately identify the patterns and processes causing hotspots, and for strategies to drive improvements that ensure device designs and fab processes are stable for production, ensuring hotspot control.
Hotspots and Process Windows
Process window qualification (PWQ) has been widely used by semiconductor manufacturers since the late 1990s to identify the limits with respect to systematic defect failures (hotspots) of a patterning process window for focus and exposure conditions [references 1-4]. However, there is a need to not only to qualify a process window, but to discover it – a need for Process Window Discovery rather than Process Window Qualification [reference 5]. We are also seeing a change in the causes of hotspots; design systematics related to layout or OPC no longer dominate as the primary source of hotspots. We are seeing an increasing effect from process systematics (Figure 1), which are related to design but are induced by process related sources (wafer non-uniformity, process variations), or, in case of multi-patterning schemes, also by interactions between the different masks.
Fig. 1: Empirical Pareto on sources of hotspots at 10nm design node.
With shrinking design nodes, we also observe that the process windows for critical layers are shrinking. This trend is highlighted in Figure 2, where depth of focus windows decrease with smaller technology nodes – though the process window is typically smaller than the overall depth of focus for a given node. These shrinking process windows, or sometimes zero process window seen in R&D, drive the need to identify how to improve or expand the process window and ultimately to control the process window during ramp and production to prevent hotspots and maximize fab yields. This has led to the introduction of the new strategy of Process Window Discovery, Expansion and Control.
Fig. 2: Depth of focus budget by design rule.
Discovery. Process window discovery uses a wafer modulated in scanner controllable conditions, such as focus and exposure or overlay [references 6,7], to induce hotspots designed to uncover susceptible structures or types. Using this information, the inspector’s sensitivity can then be maximized on the discovered hotspots to accurately identify the edge of the process window. This process window discovery method uses a broadband plasma optical wafer inspector, leveraging pin•point technology to focus the inspection care areas on the most susceptible design areas. The optical inspection is paired with e-beam defect review to efficiently find and identify the hotspots. This technique provides the sampling over both full field and full wafer to produce the ground truth of critical hotspot types and the process window for the overall litho/etch patterning process.
Expansion. Process window expansion makes use of ground truth learning to identify correlations to the sources of hotspots. We are seeing hotspot sources fall into five categories:
1) Design – Layout or OPC
2) Litho process
3) Wafer topography
4) Process variations
5) Reticle effects
By utilizing a range of process control data sources, such as CD measurements, overlay error data, film thickness and wafer geometry, fab engineers can identify the causes of hotspots. Additional insight can be gained by comparing hotspot discovery output to patterning simulations, such as those obtained from PROLITH. These correlations enable the fab team to improve their process window not only by taping out a new mask, as has been the response in the past, but also by better centering lithography and etch processes, or identifying other process improvements that reduce variations at the source.
Control. Process window control utilizes multiple inspection and metrology steps at process modules throughout the fab to identify excursions responsible for hotspot formation. Examples of process window control tactics include:
• Overlay measurements after litho detect overlay error excursions that indicate shifts in the lithography process window that can result in overlay-induced hotspots.
• Post-CMP wafer shape measurements can highlight wafers with high stress that directly relates to post-litho overlay error.
• Post-etch defect monitoring can identify process systematic hotspots, while optical critical dimension measurements can provide feedback on the etch process window.
By implementing multiple process control monitoring steps throughout all modules in the fab, engineers are able to quickly detect process window variations and implement corrective action to prevent yield loss. Additionally, by tightly controlling each process step, fabs are better able to remain within the narrow process windows needed to prevent hotspot-related excursions and ensure patterning success.
Through a comprehensive process window discovery, expansion and control strategy, the fab team can gain a firm understanding of the hotspot population and how to minimize their occurrence. By first identifying the design- and process-related sources of hotspots, engineers can then take steps to expand process windows through fab-wide process improvements, and finally to implement inspection and metrology to detect and control critical process variations over time.
References:
1. Ingrid B. Peterson et al (2005). U.S. Patent No. 6,902,855. Washington, DC: U.S. Patent and Trademark Office.
2. Shih Chieh Lo et al, “Identifying process window marginalities of reticle designs for 0.15/0.13-μm technologies,” Proc. of SPIE, Vol. 5130, 2003.
3. Zih-Wen Chang et al, “0.13-/0.15μm production reticle process window qualification procedure for 200-mm manufacturing fab,” Proc. of SPIE, Vol. 5446, 2004.
4. Daniel Chen et al, “Lithography Hotspot Discovery at 70nm DRAM 300mm Fab: Process Window Qualification Using Design Base Binning,” Proc. of SPIE, Vol. 7140, 71400R, 2008.
5. Dieter Van den Heuvel et al, “Process Window Discovery Methodology Development for Advanced Lithography,” 27th Annual SEMI Advanced Semiconductor Manufacturing Conference, May 2016.
6. Sandip Halder et al, “Inspection Challenges for Triple Patterning at Sub-14 nm nodes with Broadband Plasma Inspection Platforms,” 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, May 2015.
7. Kaushik Sah et al, “Process Window Discovery, Expansion and Control of Design Hotspots Susceptible to Overlay Failures,” 28th Annual SEMI Advanced Semiconductor Manufacturing Conference, May 2017.
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