Pushing The Limits

The constant shrinking of features is hitting some limits. What’s next?

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Ever since the turn of the millennium, researchers have been warning that wires and interconnects will have issues. Electron crashes were reported as early as 2001, and electromigration is rising to the forefront of problems at advanced nodes.

The result? Chipmakers are looking at thicker wires for the first time as a way of dealing with resistance and capacitance issues. While this makes sense from a signal integrity and performance standpoint, the effects have yet to be fully digested by the industry. What happens, for instance, when everything else shrinks but wires stay the same? What does that do to routing congestion, which is already a big problem around memories?

They also are beginning to take different approaches to building chips more seriously. Stacked die have been talked about for years, but the big stumbling block has been the cost of the interposer or the complications of stacking logic on logic. The new approaches being considered heavily leverage the push to include more third-party IP in designs, and with the cost of multi-patterning looming at advanced nodes, they’re looking increasingly promising from a cost perspective.

Semiconductor engineering always has been incremental, iterative and innovative, but it also is pragmatic. While Moore’s Law looks like a straight line to the outside world, put it under a microscope and lots of zigzagging comes into focus. Technologies that have been discarded can and are being re-used. Consider back or body biasing, for example, which went out of vogue at 65nm and has suddenly reappeared in conjunction with fully depleted SOI. There is renewed interest in bi-polar approaches, as well.

Even 2.5D is a rehash of multi-chip modules with a sophisticated interposer layer. And technologies that were developed in the past but never used are suddenly gaining attention, particularly with power now the dominant factor in the performance, power and area equation.

The result is that new designs don’t necessarily use just the latest and greatest technology and tools. In fact, some of it may have been developed decades ago. And some of the newest developments may never see the light of day in commercial implementations, even if they do hold promise in the lab or show up in test chips.

But they are requiring more changes than in the past because it’s simply too hard to push everything forward at the same rate as Moore’s Law has demanded in the past, and that’s starting to create uncertainty that chips will perform as planned, from a functional, performance and power standpoint. Add in software, and it gets even more interesting.

Industry veterans will attest to the constant need for change and re-thinking of direction. But never before have so many possible directions and alternative directions been on the table. And like most semiconductor engineering, they will all be tried and tried again in different combinations before the winning approaches come into focus.

—Ed Sperling