Raising The Stakes For IP

By Ed Sperling
As the amount of IP in an SoC increases, so do the number of players who want to strengthen their position in this market.

The big acquisitions that began several years ago over time have proved to be just opening salvos—something that was impossible to predict when this shift began. Synopsys’ purchase of Virage Logic and Cadence’s purchase of Denali, both of which occurred in 2010, were viewed as costly gambles at the time. For one thing, they were expensive—the purchase price for each was $315 million. Second, while it made sense that more companies would increase the amount of third-party IP and verification IP used to develop SoCs, the bulk of that IP remains internally sourced. And third, for all the potential upside in commercial IP, the business remains incrementally labor-intensive, making it hard to determine and achieve economies of scale.

Still, the risk-reward equation appears to have changed at 28nm. Time-to-market pressures coupled with rising complexity—a direct result of more functionality on a chip and the need to put the brakes on runaway verification NRE—has suddenly made the IP business far more attractive. Consider the following:

1. Cadence’s purchase of Cosmic Circuits last week, which puts it into direct competition with Synopsys for standard IP;
2. Tensilica’s move to create imaging subsystems, complete with software;
3. Imagination Technologies purchase of MIPS last month, along with ARM’s beefing up of its Mali graphics engine;
4. A renewed focus on qualifying IP by companies such as Atrenta and TSMC, and effectively testing it by companies such as Mentor Graphics.

Taken as a whole, these developments indicate much more attention being paid to the IP business, both by the companies involved and their customers.

“In the last 9 to 12 months the competitive landscape definitely has changed,” said John Koeter,” vice president of marketing for Synopsys’ Solutions Group. “The next phase has begun. To be effective, you have to ‘go big or go home.’ There is still a legitimate need and market for customized circuits and small IP companies that provide that will continue to play an important role. But the rest of the market will be dominated by bigger companies.”

Economies of scale
The biggest driver in all of this is the shift to SoCs from ASICs and the amount of functionality now sitting inside of these chips. Even Intel is betting on SoCs for future growth and using third-party IP in its chips, according to several sources.

“This is a $4 billion market and it’s growing $160 million a year,” said Koeter. “The compression of schedules driven by mobile and the pressure of time to market coupled with budget pressure and an increasing focus on software has forced a market shift to outsourcing. But from our perspective customers want to buy as much IP from a single source because they can consolidate their purchasing power, ensure consistency in the relationship, and that way they have one vendor to go to if there is a problem.”

Another less obvious reason is the economics of the IP itself. Even with standard IP, which increasingly is where the war is being fought, characterization of the IP becomes increasingly difficult. There are almost unlimited scenarios for implementing IP, which can cause physical effects in other parts of an SoC. The only way to really understand that is to test and re-test the IP, which costs money. That cost, in turn, needs to be amortized over a larger customer base than just a handful of customers.

Both Synopsys and Cadence also have a hand in analog IP. Kevin Yee, product manager for Design IP at Cadence, believes the analog/mixed signal market will prove to be a highly competitive area, as well.

“A lot of this is being driven by the mobile and consumer market,” said Yee. “Part of that is architecture and part of it is implementation. And part of it is about unique ways of keeping the cost and the power down. What made Apple so successful was that it created a complete ecosystem. Partnerships out of TSMC, GlobalFoundries and ARM are aimed at building that same kind of ecosystem. It’s not just about IP. It’s about how it fits into a system.”

Yee said that in the past, that involved almost exclusively digital IP. Increasingly it is a mix, in part because analog IP is so much harder to develop at advanced process nodes.

What’s in the black box
Another approach to dealing with integration and characterization—and to make sure everything works as planned—is to develop more than just an IP block. All of the major IP vendors have begun adding libraries and detailed data. And as ARM CTO Mike Muller has said, “The Legos get progressively larger.”

Witness Tensilica’s move this week to roll out a complete imaging subsystem. The benefits of a processor designed for a specific purpose are readily apparent even in ARM’s big.LITTLE architecture, where less compute-intensive functions are assigned to a smaller processor core. In a subsystem, there are the added benefits of software and libraries, with the integration and optimization already done.

“In imaging we’re heading to 20 megapixels in a smart phone, and you will want a video frame rate that allows you to stream high definition video,” said Chris Rowen, chief technology officer at Tensilica. “So by the end of the decade silicon will be five times better but the problem will be 25 times harder. If you use CPUs, you won’t get the necessary performance or enough energy efficiency. A GPU is somewhat more efficient—maybe two or three times better—but it’s not nearly as efficient as an image processor. What’s changed is the rise of application domains to significance, where you incorporate the hardware and software.”

Using specialized processors inside of SoCs is nothing new. In complex SoCs it’s not unusual to see a variety of DSPs, CPUs, GPUs and embedded processors for specific functions. In many cases, it makes sense just from a latency perspective not to have all data synchronized. But using subsystems containing processors has been slow to catch on in areas other than audio and video processing. And while most companies predict this is the future direction, questions remain about where these subsystems will catch on and when.

“As chips get bigger you definitely will see more subsystems,” Rowen said. “Without them software will become more difficult to test and deploy. And well-tested subsystems that follow an object-oriented development model can be far more reliable than one do-it-all processor that has to time slice. There will be a benefit in modularity because of proven independence of subsystems.”

Making sure it works
None of this is a guarantee that IP will work, of course, and even for standard IP there are indemnification agreements. But the reality is that the more IP is used, the more effectively it can be characterized.

For example, the foundries have been working with IP suppliers to put their stamp of approval on that IP. In some cases, that approval is as simple as making sure it can be synthesized properly. But TSMC also has been working with Atrenta to qualify it more thoroughly, most recently for power.

“What’s clear is that power reduction is a chip-level opportunity,” said Mike Gianfagna, vice president of corporate marketing at Atrenta. “For that you have to consider the power consumption of an IP block. But the problem is that can be misleading because it may not be what you get with the system implementation. There are ways to come up with reference IP that takes that into account, but it’s a lot more complicated. You’ve got physical time and effort and cost, and the IP providers resist that because they want to sell as much as possible. If you really characterize their IP, that limits the market potential.”