Re-Using IP In Packaging

The biggest advantage in advanced packaging is still missing, but that’s expected to change.


For the past decade, the promise held forth by advanced packaging was that it would allow chipmakers to mix and match analog and digital IP without worrying about the process node at which they were developed or the physical interactions between components.

This is a big deal when it comes to analog. Analog IP doesn’t benefit from node shrinking the way digital logic does, and in many cases the analog IP that is included in finFET-class chips is really a combination of analog and digital circuitry. But the need for more analog content is growing, particularly as the IoT and IIoT seek to bridge the physical and the digital worlds. All of the sensors are analog, or at least have an analog component to them. Being able to choose sensors to include in a package based upon price, performance, power and other physical characteristics would be of huge benefit to chipmakers.

The problem, as OSATs, foundries and chipmakers all have discovered, is the IP needs to be created specifically for these advanced packages. That will take time. Just re-using commercial IP developed for planar chips may work in some cases, but even that IP has to be characterized more effectively. In the case of analog IP, for example, multiple types of noise and thermal effects can affect overall performance. Likewise, signal routing, inter- and intra-chip bandwidth/throughput, and the min/max voltage of a block (or even nearby blocks) can impact how that IP behaves.

The best approach is to design IP specifically for use in advanced packaging, which is why most of the fan-outs and 2.5D implementations have included IP developed at the same process node as the most advanced logic in those packages. But the real advantage of advanced packaging is to be able to pick from a menu and then cobble together a solution quickly for a specific market application, essentially turning a package into a platform, where 95% of the chip is already built.

This platform approach was suggested in the past, before advanced packaging was firmly established. The fundamental concept is that while requirements differ for various vertical markets, the majority of components are the same from one market to the next. The difference is in how they are used and sized. So there are still one or more processors, memories and I/O blocks, but actual configurations will vary. A SerDes block will require higher higher performance for a cloud-based server than for a smart refrigerator, for example. And a car’s back-up camera sensor will need to be on within a fraction of a second to avoid accidents, while the sensors monitoring the temperature of the car’s cabin can take much longer to boot up.

As use cases are established, these platforms will be developed for different markets. Advanced packaging is just beginning to go mainstream, which means that IP specifically developed for 2.5D or a fan-out wafer-level packaging is being designed and implemented now. That IP may require less power than it would for an ASIC or an SoC, because the amount of power necessary to drive signals through an interposer, for example, will be lower than trying to force those signals through skinny wires that span the length of an SoC.

After that IP is developed and enough solutions are built around it, packaging will roll into the second phase, which according to plan will significantly reduce the design time necessary to design chips. This is the first phase in what has loosely been defined as “mass customization,” and it will sharply reduce the time it takes to develop solutions for different markets, as well as the time it takes to validate and verify these solutions. From there, it’s expected that advanced packaging will begin snowballing—particularly for markets that cannot support a custom ASIC, which at this point is most of them.

Behind the scenes, the entire industry is taking steps to prepare for these changes. The expectation is that if the market rollout of advanced packaging continues unabated, it could have far-reaching implications for the entire semiconductor ecosystem. The only question now is when.

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