Systems & Design
WHITEPAPERS

Ready For 3D-IC

A look at the challenges and solutions for verifying and testing IC designs targeted for 2.5D or 3D packages.

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This technical presentation describes the challenges and Mentor’s solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers. To download this white paper, click here.



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