Recalculating The Cost Of Test

The cost of test is rising.

For decades, test was limited to a flat 2% of the cost of designing and manufacturing a chip. Today, no one is quite sure what that cost really is, and there doesn’t seem to be any single formula for determining it. In some cases, there isn’t even a sense of urgency to finding out.

Several significant changes are occurring that make any formula difficult to calculate, and it could remain that way for years to come.

1. Reliability is now a variable cost. As more chips are used in safety-critical applications such as automotive, and as they are used in mission-critical applications such as cloud-based servers, the underlying cost structure has become much more complex. Consider automotive applications. While it’s annoying and inconvenient if a power window actuator stops working, it’s a whole different matter with chips used in the drive train. In fact, there is a liability trail all the way back to the initial design for those chips, which are supposed to last for more than a decade.

As a result, the cost of test for an actuator will be significantly lower than the cost for an engine accelerator or a chip that controls automatic braking or lane drift. And the cost of a failure in a data center is so high that customers are willing to pay extra for a battery of testing, inspection, metrology, burn-in, and just about any other step that can improve reliability. That extends out on both sides of the design-through manufacturing flow, as well, starting in the design phase where more verification, simulation and lab-based testing is done, and into the field where those chips are monitored throughout their lifetime.

2. More components make test-in-context essential. There’s system test, and there’s system of systems testing. While system test is well understood and done in the fab, the interactions of different systems can create problems even for chips within spec. Variation, edge placement errors in lithography, and a host of other manufacturing effects may not show how a device will behave in the context of other devices, and as they age and interact, those effects may become worse.

Testing for those issues requires a deep understanding of how chips will interact with other chips and systems. And where AI/ML is concerned, it also requires in-depth knowledge of how those devices will change over time as they self-optimize. This can be tested for, but it takes time, and that time requires an investment of both money and other resources that isn’t considered part of the typical testing regimen.

3. Smaller batches of customized designs are harder to test. Until the finFET era, most designs were monolithic and planar. After 7nm, a growing percentage of high-end designs have become multi-chip implementations in some sort of advanced package, and they are increasingly heterogeneous. There are multiple IP blocks, multiple processing elements, and multiple memory types, and very few of them are being produced in batches of 1 billion units or more.

As a result, it takes much more effort per chip, and per dollar, to fully test these devices and understand all of the possible interactions, and a significantly higher percentage of the total development cost to make sure chips don’t fail within the first six months of use in the field. Some of this can be moved to the lab, and some can be handled with better simulation, emulation, and much more extensive verification, particularly with formal tools. But the bottom line is there are so many unique implementations that even developing a test probe or inspection routine is more challenging.

So what does this mean for the cost of test? The answer is that no one is quite sure. ATE may stay at a flat 2%, but the real cost of test now needs to be computed based on volume, complexity, and the cost of a failure. As chips are used in more critical applications, and across a wider number of devices, that cost can vary greatly, and so can the real cost of test.