How to improve quality and efficiency in a high-level design flow.
A team at Renesas Electronics Corporation found that they were significantly reducing the time advantages of their High-Level Synthesis flow due to bugs in their SystemC code and equivalence problems due to design changes. It was taking too much time to find and debug these issues and some bugs were slipping into the generated RTL. To solve these challenges, they added SLEC®, which is the formal equivalence checking tool within the Catapult® verification solution. Learn why Renesas has determined that SLEC is a must-have application for their high-level design flow and how it improves verification quality and efficiency by reading this white paper.
To read more, click here.
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