RF, MEMS, Photonics Driving 3D Stacking

By Pallab Chatterjee
At Semicon West, a number of the key speakers and TechXPOTs were talking about current products being assembled and shipped with 3D technology. 3D die stacking is no longer a technology of the future. In fact it has been here for many years and has been used in millions, if not billions, of consumer, commercial and high-reliability designs.

The two leading technologies that have embraced this technology are memories and MEMS. Memories have used stacked die (back to top stack) with wire bonds for decades and have shipped literally billions of parts to the marketplace. These parts have been both DRAM and non-volatile memory technologies. Memory technologies, due to their high I/O and bandwidth requirements, are still a key driver of the 3D technologies. Many designs are being implemented with TSVs, and utilizing a silicon interposer layer. The goal is to get multiple device types connected together, such as CPUs, MEMS, and RF, and not just multiple instances of the same chip.

MEMS subsystems are also a known technology for multi-die stacking. A typical three-layer stack would be a MEMS gyroscope, a MEMS accelerometer and a signal-processing chip to interpret the output of the two MEMS sensors and interface to a standard logic design. These designs are currently available from many companies in the United States and Europe and are able to meet consumer-level price points. The Nintendo 3DS, for example, uses a MEMS gyroscope from Invensense, which is a mixed MEMS and CMOS product. Similarly, a control IC appears in the Nintendo Wii motion-plus controller. All are considered cost-effective and reliable.

On the high-performance side, Xilinx is shipping array-based designs. These SoCs feature four bit-cell blocks of Virtex-7 cores distributed over a silicon interposer to provide the high speed interconnect. The technology uses TSVs, microbeads, microbumps. C4 balls, BGA solder balls, and multiple 28nm FPGA bit-slice chips. Xilinx’s new stacked silicon interconnect technology enables a single FPGA device to deliver more of the FPGA resources that customers need—logic, memory, serial transceivers and processing elements—while providing industry-leading capacity and bandwidth performance. The technology allows for multiple FPGA die to be combined and provides up to 100x improvement in inter-die bandwidth per watt over conventional approaches (See fig. 1)

IMEC of Belgium and Leti of France both presented new directions for integrating core processors and face-to-face stacked memory that act as cache RAM. These systems also will include RF die stacked face to face on the silicon logic. Extended research will lead to further integration of stacked interposer with passives and advanced RF components—inductors, capacitors and large resistors—with these die and finally lateral communication interfaces such as silicon lasers and other nano photonics.

These photonic interconnects have been the internal baseline for 1Gb/sec. and higher communication links for long distances for many decades. The localized heat and micro-machined optics (gratings, etc.) have been well addressed and now allow for integration with other circuits. The work at IMEC is focusing on integration of these lateral signal paths with vertical TSV-based connectivity. The testability and reliability advantages of using tested “known good” die is driving this method forward in systems.

The next big driver in multi-processor systems is the integrated APU, which has a CPU, GPU, and memory controller in a single die and connected directly to system memory with TSV technology. This structure, which is not using a silicon interposer, features tens of thousands of connection points to give very high-bandwidth and low-latency connectivity to both cache and local main memory in a single unit. These systems will be available in end products shortly and are the key technology that will realize the next generation of tablet and smart phone products.