Self-Driving Cars At CES: The Future Of Transportation Is Here

CES 2018 attendees will get a new kind of tech demo in just a few weeks. When they hail Lyft to take them from the Las Vegas Convention Center across town, it will be a fully automated point-to-point vehicle getting them there.

While we marvel now, today’s novelty will be tomorrow’s norm, though questions about the safety of autonomous driving persist. For the CES demo, a backup pilot will be in the driver’s seat… just in case.

Transitioning from pilot-assisted to fully-autonomous vehicles heightens the role of vehicle safety. The more the onboard network takes control of the vehicle, the more drivers and passengers like those from CES in Lyft cars expect multiple levels of safety to prevent accidents.

ISO 26262, the international safety standard, offers a rich set of methodologies to measure fault-tolerant safety in autonomous vehicles, including an IP block’s functional safety. The failure modes, effects and diagnostics analysis (FMEDA) technique outlines standard specifications for functionality and failure modes of IP elements. They cover the effect of a failure mode on product functionality, the ability of automatic diagnostics to detect failure, the design strength and the operational profile, including environmental stress.

A system implemented in an autonomous vehicle should maximize the diagnostic coverage of IP elements and offer high functional safety by handling safe, detected and undetected faults appropriately. Programmable architectures, particularly embedded FPGAs, enhance the safety of the vehicle as a system because of their programmable nature.

Functional safety is one benefit of eFPGAs. Other advantages include lower latency, better security, high bandwidth and reliability. In fully autonomous and advanced piloted vehicles of the future, there will be dozens and even hundreds of distributed CPUs. Peripheral processing functionality to tie together automotive subnetworks can be well served by an eFPGA IP.

Count on an eFPGA in an SoC to host in-flight functions. Better yet, it can host extensive hardware diagnostic routines orders of magnitude faster than software-based diagnostics, increasing fault coverage. eFPGA IP offers advantages such as minimizing CPU interrupts by writing to a CPU cache rather than off-chip memory. BIST circuits required in CAN designs, often amounting to 10 to 15% of total ASIC circuitry, can in many cases be eliminated, since circuitry supporting BIST can be programmed within the eFPGA. Additionally, an eFPGA can offer on-chip probing functions for diagnostics.

Possibly an eFPGA’s most attractive feature is its programmatically to aid in the safety life cycle ––automotive OEMs can update already deployed systems.

Whether an automobile is a piloted vehicle or an autonomous vehicle piloting through Las Vegas traffic with only minimal human assistance, the need for hardware acceleration in networked transportation system is skyrocketing. The best choice is an eFPGA IP implemented inside an SoC as hard IP. It optimizes real estate and power efficiency, and includes configurable capabilities.

Those lucky CES attendees will cruise down Las Vegas Blvd in self-driving BMW 5 Series cars. It won’t be long before every car dealer can take prospective buyers on a similar ride, most likely, with an onboard eFPGA.

The future of transportation is here.