Semiconductor Test Faces Technology Shifts In The AI Era

The surge in data-rich applications shows no signs of slowing down, fueling significant evolution within the global semiconductor industry. This insatiable demand for data necessitates a comprehensive ecosystem involving sensors and systems to capture data, networks to transmit it, and storage and processing power to analyze it.

Successful deployment of these applications relies on the development of increasingly complex semiconductor technologies. Ensuring the quality of these devices requires test strategies that optimize efficiency. By integrating automated test equipment (ATE) and system level test (SLT), we can support the evolving needs of AI and high-performance computing (HPC) applications in both data centers and edge devices.

AI applications at the heart of the data deluge

AI applications are proving to be a significant growth driver, and the semiconductor industry continues to prosper and build towards a target of $1T in revenue by 2030 (see figure 1). As AI applications evolve and become more complex, requiring more and more compute resources, so must the underlying technologies; this is illustrated by the exponential increase in transistors per microprocessor in increasingly complex devices.

Fig. 1: Exhibit from “The semiconductor decade: A trillion-dollar industry”, April 2022, McKinsey & Company, www.mckinsey.com.

The demand for high-performance computing is essentially doubling every 3.4 months – faster than Moore’s Law – driving the trend of heterogeneous integration, or multiple cores integrated into a single advanced package. With these advances, the overall testing universe has become significantly more complex.

In addition to the number-crunching processors such as CPUs and GPUs, there is also a demand for very high-speed data center interconnects (DCIs) to efficiently move all this data around. DCIs connect multiple data centers over any distance, including sub-sea and up to the longest intercontinental routes, with fast, low-latency optical links, creating a slate of new test challenges. For example, DCIs may rely on coherent optics within the communications die for data transfer rates of up to 800 Gb/s per wavelength. Testing such die with these co-packaged optics can create a unique opportunity for ATE.

Edge AI multiplies the demands

AI algorithms excel at interpreting unstructured data such as language, images, sounds, temperature and facial recognition, making them highly effective in environments where users encounter real-world challenges. Deploying these AI applications in a centralized cloud or enterprise data center is often unfeasible or inefficient, due to limitations related to latency, bandwidth, and privacy concerns.

The answer is edge AI – the deployment of AI applications in devices located near users, at the edge of the network, instead of in centralized cloud or data centers. This allows AI processing to happen locally, close to where the data is generated, and is especially useful in environments where real-time responses, bandwidth limitations, and privacy and regulatory concerns make centralized processing unattractive.

The edge may be a smartphone, laptop, autonomous vehicle, or IoT device like a thermostat or security camera. Industrial applications are adopting edge AI for a range of devices on the factory floor, handling predictive maintenance, quality control, and real-time decision-making. Other examples proliferate in healthcare devices, smart cities, unmanned aerial vehicles – the edge is wherever computing needs to be. Often edge AI and data center AI can work alongside each other, providing the right answer for specific applications.

All these applications create a diverse set of new demands on test strategies.

Test strategies adapt and innovate in step with chip performance

To keep up with the increased need for chip performance in this era of AI, HPC, and fast data interconnects, advanced ATE systems now incorporate more intelligence and flexibility. They support a wider range of test protocols and can quickly adapt to different test scenarios. Enhanced ATE capabilities include parallel or multi-site testing, high-frequency signal generation and analysis, and real-time data processing. These features help reduce test times and improve throughput, which is crucial as chip performance demands continue to rise.

For example, multi-site testing involves testing multiple devices simultaneously on a single test setup. This approach significantly improves throughput and reduces overall test costs, which is especially important as semiconductor devices become more complex and volume production increases. Concurrent testing allows different tests to be performed in parallel on the same device or across multiple devices. This strategy maximizes test equipment utilization, speeds up the testing process, and helps meet ever-shorter time to market requirements. Ultimately, multi-site testing and parallelism reduce the overall cost-of-test per unit tester.

High-frequency testing ensures that devices can handle the required data rates and signal integrity demands that accompany AI, HPC, and fast data interconnects. Testing for parameters like jitter, phase noise, and harmonic distortion is critical for ensuring reliable performance in high-speed applications.

Adaptive testing involves dynamically adjusting test conditions based on real-time data and feedback during the testing process. This approach can optimize test time and resources by focusing on critical areas and reducing redundancy. Adaptive methods are particularly useful for handling process variations and ensuring consistent product quality, especially in high-volume manufacturing environments where variability can impact yield and performance.

Coupling ATE and SLT

ATE may also be paired with SLT, a test method that replicates the actual usage environment of a given device to detect issues that may not otherwise be apparent, such as power management failures, signal integrity problems, and thermal performance issues (see figure 2). This approach goes beyond traditional wafer and package testing to ensure that chips perform as expected when integrated into their final applications, like smartphones, data centers, or automotive systems.

Fig. 2: ATE and SLT test time.

Achieve full test coverage to ensure quality while balancing cost of test

As products move towards high-volume manufacturing, tests can be shifted in the test process to reduce test time without sacrificing test coverage. This is known as a “shift-left” and “shift-right” strategy. Shifting tests left involves moving testing earlier in the design and manufacturing process, (e.g., during wafer inspection and partial packaging) to maximize known good die (KGD). Conversely, shifting test to the right extends test coverage later in the manufacturing process such as final test, expanding the ability to detect defects; this maintains quality levels while reducing costs with higher parallelism testing. Together, these strategies ensure the optimal combination of quality and yield throughout the entire manufacturing process, ultimately optimizing the overall cost of quality (see figure 3).

Fig. 3: Shift test coverage to optimize cost of quality.

Ensuring wireless testing capabilities

It’s important to note that keeping up with all these AI nodes also requires wireless networks to evolve – the increase in data being processed means the networks must be faster and more efficient. Consequently, over-the-air (OTA) testing is emerging for wireless devices and components, particularly with the rollout of new communication standards like 5G and upcoming 6G technologies. OTA is closely associated with mmWave, which can help relieve congestion in dense urban environments like stadiums and airports. Its use introduces antenna-in-package (AiP) devices that present new challenges for test, as OTA operates at a higher frequency and requires greater bandwidth.

OTA testing evaluates the performance of devices without direct physical connections, simulating real-world conditions. This is crucial for ensuring the reliability and performance of wireless components, such as antennas and transceivers, in their operating environments. OTA testing helps detect issues related to signal propagation, interference, and environmental factors that might not be visible in traditional wired tests.

Introducing AI to the testing process

AI also plays a pivotal role in optimizing the testing process. By leveraging data collected during testing, machine learning and AI can help identify patterns, such as which components fail most frequently, under what conditions, and when. This insight allows for the creation of Pareto charts that pinpoint the most common failure elements, facilitating trend analysis, improving test processes, and enabling tests to be moved around. Common failure elements can be tested early in the process until they become stable; that test can then be moved to a later point in the test flow (for example, moved to SLT) if the right balance between coverage, quality, and cost can be achieved.

For example, AI algorithms can detect anomalies that traditional testing methods might miss, or reduce test time by focusing on the most critical parameters. This data-driven approach helps improve test coverage, reduce costs, and accelerate time-to-market for new semiconductor devices.

Semiconductor test is the foundation of AI application success

Enabled by new advancements in semiconductor architectures and super-fast 5G networks, data-rich AI and edge computing applications are introducing complex conditions for testing. Test leaders must develop advanced and flexible strategies to meet the increasing demand for chip performance in AI, HPC, and fast data interconnects. Modern ATE systems must be more intelligent and adaptable, capable of handling complex, high-speed devices and supporting diverse test protocols.

As the worldwide demand for data continues to grow exponentially, it’s ATE innovation that enables semiconductor manufacturers to keep pace with rapid advancements in chip performance and the increasing complexity of modern semiconductor devices. With a smart, flexible approach to test, the industry can ensure the quality, reliability, and performance of the next generation of semiconductor technologies.