The growing demand for scan and the need for new DFT approaches as individual transistors become complex 3D structures.
In the semiconductor fabrication process, engineers continue to innovate, enabling smaller transistors and higher density circuits. The transition to finFETs allowed 7nm and 5nm processes to realize circuits of amazing density, and the progress of nanosheet transistors provides confidence in the future advancement of digital circuit cost reduction and performance improvement.
As individual transistors become complex 3D structures, the intricacies of device failures and the exponential growth in transistor count will continue to evolve for leading edge processes, creating quality challenges as new devices are manufactured. Test companies must provide cost effective means to establish the production quality of ICs.
Tucker Davis, product manager for Teradyne’s flagship tester, the UltraFLEXplus, discusses the growing demand for scan and the need for new DFT approaches to scan, associated power challenges, whether structural test can find sufficient defects or is System Level Test required, and how scan and device test data can be used to improve yield.
Watch the video here.
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