Semiconductor Testing Unlocks Increasing Levels Of ADAS

Today’s advanced driver assistance systems (ADAS) require unprecedented computing power – tasked with processing an incredible amount of data from sensors in real-time, making split-second decisions, and ensuring the safety and comfort of passengers. The challenge is fluid and, as vehicles ascend from one level of autonomous driving to the next, computational demands will rise exponentially.

The automotive industry is tackling these challenges head-on, shifting to more sophisticated and power-intensive computing architectures. ADAS designs include advanced nodes at and below 7nm process architectures and integrate improvements like 3D packaging and chiplets. These complex systems demand a comprehensive approach to quality assurance and testing, tailored to guarantee performance standards in an industry charged with meeting a zero-defect commitment. Semiconductor testing partners must deliver a holistic solution, ensuring the automotive sector can reliably advance to higher levels of autonomy while maintaining stringent quality controls.

ADAS evolution increases compute demands and design challenges

Levels of ADAS. (Source: SAE)

As ADAS technologies evolve, there is a surge in demand for digital integrated circuits (ICs) and high-speed interfaces. The journey toward full autonomy relies on deploying an ever-increasing number of sensors, including radars, cameras, LiDAR, and ultrasonic sensors. As the eyes and ears of ADAS, these sensors generate vast amounts of data. The escalation in data generation is not trivial; it represents a foundational shift in how vehicles perceive their environment, requiring robust data handling and processing capabilities.

Power and heat add new complexities

Increased compute workloads, in turn, create challenges in power consumption and heat dissipation. As vehicles move closer to Level 5 autonomy, the power requirements are expected to jump from a modest few watts to hundreds of watts or more. This necessitates innovative solutions for heat management to protect sensitive components and ensure reliable operation over the vehicle’s lifespan. Options may range from passive and active cooling mechanisms to more advanced thermal management techniques, complex system elements that add to the need for design – and testing – know-how.

Levels 1 and 2 systems typically require very low power levels. Even so, this represents a power increase over vehicles without these systems, called Level 0 or no automation. Power consumption jumps significantly with the higher automation of Level 4 ADAS, and the full autonomy of Level 5 requires exceptional computational power to continuously process data from multiple sensors in real-time, posing significant challenges for power management and efficiency.

While full autonomy (Level 5) remains an aspirational goal, lower level ADAS capabilities are already operational in today’s vehicles. As the requirements for ADAS continue to escalate, they place greater demands on both the in-car technologies and the testing systems that ensure their efficacy.

With the steady evolution of ADAS, the pressure is on, particularly as carmakers embrace the role of chip designer. They’re collaborating with chipmakers and foundries, differentiating their designs and prioritizing the user experience.

But taking on the chipmaker role has its own challenges, and today’s advanced nodes are a new variable. They offer the enhanced performance required for advanced automation – yet they are highly complex and represent certain unknowns, with some design scenarios not fully understood or verified. Their complex process architectures below 7nm will shrink further to 5nm, 3nm, 2nm, and beyond, continually introducing less mature technology into development cycles and timelines.

Test coverage is essential

Each generation of semiconductors contains billions more transistors that must be tested and verified. At the same time, chips deployed in automotive applications are held to a much higher standard than those integrated into consumer or industrial grade products. Automotive performance requirements are significantly more stringent, grounded in the awareness that costly product recalls can impact perceived vehicle safety, damage brands, and increase budgets.

Meeting the challenge requires better understanding of the failure models of advanced nodes, and uncovering them via an effective test process. Historically, that testing process combined tri-temperature test conditions with automatic test equipment (ATE), along with burn-in and system level testing (SLT). Newer, more advanced nodes are continually being used in automotive applications, pushing the need for comprehensive test. The goal is to ensure these advanced chips can operate reliably in systems that are on the road for decades, making it a testing industry priority to continually refine ATE processes and fault models that identify and address potential risks.

On one hand, there is a critical need for comprehensive test coverage. This involves a detailed application of ATE processes to ensure each chip’s functionality and reliability in real-world automotive environments. On the other hand, flexibility in testing is crucial to balance economic considerations and adapt to dynamic changes, such as improvements in chip yield. A flexible test strategy, including the ability to move test coverage and test programs between insertions is imperative to maintaining both quality and test economics.

System Level Test improves quality

It’s important to recognize that as process nodes continue to shrink, even 99.5% ATE fault coverage leaves a large number of transistors untested. Today, advances in SLT can help find the faults in the remaining 0.5% of untested transistors.

Utilizing SLT as a third test process step, following wafer and package test, enables the carmaker/semiconductor manufacturer to test software and hardware together to validate connections between IP blocks in a manner that isn’t otherwise practical. The process provides an easier way to test complex interfaces, which is critical for systems with a high number of interactions among power, clock, and thermal domains, as well as software and hardware.

Teradyne’s Titan SLT platform provides an example. By exercising devices in mission mode, it tests the complex interactions where faults may exist; this delivers the additional test coverage needed to meet stringent end-customer failure rate requirements for improved product quality.

Complexity at every turn

As the automotive industry accelerates toward fully autonomous driving, progression through the levels of ADAS is rife with new technical challenges. From basic assistance features at Level 1 to the full autonomy of Level 5, the road to autonomy is marked by significant milestones in sensor deployment and computational demands – which have significantly increased the complexity of automotive system design and testing.

Overcoming these hurdles requires technological innovation, strategic collaborations, and a commitment to rigorous testing and quality assurance. By addressing the increased demands for sensors, computing power, energy efficiency, and testing, the industry can pave the way for the reliable and safe adoption of autonomous vehicles.

In this journey, the role of optimized testing partners becomes ever more critical, providing the assurance that as vehicles become more autonomous, they remain safe and dependable for all users.