Shift Left Power-Aware Static Verification

Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques can introduce critical bugs into a design, especially when the power-management infrastructure interacts with signals that cross clock or reset domains. This can create additional clock-domain crossing (CDC) or reset-domain crossing (RDC) paths or break the synchronization of pre-qualified CDC/RDC paths. This may also result in subtle bugs escape to silicon which traditional CDC/RDC tools cannot catch. This blog highlights the challenges and describes the UPF aware static verification solution for clock and reset domain crossings.

Design trends impacting static verification

Figure 1: Design trends indicating increasing number of clocks, resets, voltage domains and shutoff domains

Solution ensuring consistency between verification and implementation

Figure 2: Solution for UPF aware CDC/RDC

In the figure above, B1 and B2 are two different blocks each having different resets. When only RTL is read, if rst_A asserts first, even if the clocks are same, it is an unsafe structure because of the asynchronous rst_A assertion. When you read in the UPF along with the RTL, power domains crossings are created. Power domains are closely tied to the resets since the user needs to power down and wake up based on the power on reset. The UPF can have isolation strategies based on which isolation would be instrumented at the power domain crossings. The same ISO enable can act as a qualifier for RDC since resets are tied to power domains and now it becomes a safe structure. So, in the case where only RTL is read, the user would see an unsafe structure whereas if RTL+UPF is read, the user would see a safe structure and would not have to go through the pain of analyzing the violations. Another scenario is if the ISO qualifier is not connected in the RTL. Now, since the source and destination clocks are different, it becomes a CDC crossing and is a missed bug. This therefore necessitates the need for a UPF aware CDC/RDC solution.

Figure 3: Consistency between what is implemented vs. what is verified

One of the biggest advantages of using this solution is that it does the actual instrumentation of the low power structures in the design. Another advantage is that this solution ensures that the verification matches with the implementation. UPF interpretation must be consistent throughout the flow and this is what this solution provides.

Isolation precedence rules should have the same consistent interpretation across the entire flow. In Figure 3, there are multiple isolation policies being written for the same port P. If the policy with enable en2 gets applied, it would create an asynchronous crossing since source and sink are in different clock domains and would cause a CDC bug. Since this technology uses the VC LP UPF parser for isolation instrumentation, it guarantees that the UPF interpretation matches with the implementation.

The VC LP solution has been designed to address the needs of growing design sizes and complexities. It uses high speed engines and is production proven at 150+ customers. It provides a consistent design behavior and flow using industry leading implementation and signoff solutions. The UPF aware CDC/RDC verification technique described here will “shift left” the verification of low-power SoC designs, as well as make the verification robust enough to prevent subtle bugs escaping into silicon.