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Short-Circuit Ruggedness In SiC MOSFETs

Differences in the short-circuit behavior of SiC MOSFET and IGBT devices.

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Trench-based silicon carbide power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) represent a dramatic improvement in the Figure of Merit (FOM) values of power conversion switching devices. As a result, outstanding system performance is achieved, enabling higher efficiency, power density, and reduced system cost for many applications.

Today, for major target applications for SiC (Silicon Carbide) MOSFETs such as solar energy applications or chargers for electric vehicles, a short-circuit handling capability is not a must‑have criterion. However, for applications like motor drive, you can find the SiC MOSFET’s short-circuit withstand time in the datasheet. This blog introduces you to the differences in the short-circuit behavior of SiC and IGBT (Insulated Gate Bipolar Transistor) devices, and how the short-circuit ruggedness of CoolSiC MOSFETs is accomplished.

The difference between an IGBT and SiC MOSFET during short-circuit events

First of all, we have to look into the actual short-circuit destruction mechanisms and the background for the differences between IGBTs and SiC MOSFETs.

For IGBT, one failure mechanism is based on a too-high leakage current after the stress pulse, which then leads to thermal runaway following the short-circuit pulse. Luckily, based on our existing experience and knowledge of SiC devices, we can rule out this type of failure mode.

In a typical short-circuit event the full (DC-link) voltage is applied to the device, as is the current defined by the load impedance and the output characteristic of the semiconductor. So, a high voltage and a high current, happening at the same time, leads to a very high power loss and thermal stress in the device. As expected, thermal destruction is the key limiting factor and the actual melting of metal layers is one of the failure modes observed. The duration of such an event is in the range of microseconds.

In the case of silicon carbide devices, various other findings are reported as well, for example, the occurrence of gate shorts after a successfully passed short-circuit event [1].

Another important observation is that under short-circuit conditions, the temperatures within a SiC chip are substantially higher with a different distribution compared to IGBTs. Higher temperatures occur because the peak currents are also substantially higher – as a ratio of the device rated current – than for IGBTs which benefit from saturation effects. MOSFETs are designed to have a very low RDS(on), which is achieved by using short channels and a limited JFET (Junction Field-Effect Transistor) effect. The result is that the SiC MOSFET peak current can be about ten times the nominal device current. With an IGBT this value might be only four times the nominal current. This happens in both cases immediately after the short-circuit starts (see figure 1). Even though later on the current drops to a value that can be safely turned off (see dashed line in figure1), the overall temperature can still rise here as well.


Fig. 1: The typical short-circuit waveforms of a SiC MOSFET with 45 mΩ

As the short-circuit time and resulting power loss are in the range of 2–3 μs, the entire chip heat capacity cannot be used for a SiC MOSFET. Also, the heat is generated almost completely in the very thin drift zone that is close to the surface of the chip and the isolating oxide layer and top layer metallization. Figure 2 depicts this situation and compares it to an IGBT. In the high-voltage silicon device, the peak temperature has a lower amplitude and is located more in the bulk of the device. Thus, different failure modes will occur and so for SiC MOSFETs, other mitigation measures are in place to adjust the short-circuit behavior of the device.


Fig 2: A schematic temperature distribution after a short-circuit event of an IGBT (left picture) and an SiC MOSFET (right picture).

How the short-circuit ruggedness of CoolSiC MOSFETs is achieved

It is important to reduce the peak current of SiC MOSFETs during a short-circuit condition. This can be achieved by a more pronounced JFET effect of the p-body regions or a reduced gate-source voltage VGS. Further ideas exist, as presented in [2]. However, all of them have a negative impact on the on-resistance. Thus, a deep understanding of the system requirements and behavior is needed to derive potential device-related measures and system innovations [3] to deal with short-circuit events while maintaining the extraordinary performance of silicon carbide under nominal operating conditions.

If the short-circuit withstand-time is to be specified in the datasheet, it is mandatory to implement measures to ensure that the production parts cohere to this performance. Here at Infineon, we do this with a 100% production test on all products before shipment.

References:

[1] C. Chen, D. Labrousse, S. Lefebvre, M. Petit, C. Buttay and H. Morel: Study of short-circuit robustness of SiC MOSFETs, analysis of the failure modes and comparison with BJTs. Microelectronics Reliability, Vol. 55, 2015

[2] H. Hatta, et al.: Suppression of Short Circuit Current with Embedded Source Resistance in SiC MOSFETs. Materials Science Forum, Vol. 924, pp. 727–730, 2018

[3] M. M. Bakran, S. Hain: Integrating the New 2D ­– Short circuit detection method into a power module with a power supply fed by the gate voltage. IEEE 2nd Annual Southern Power Electronics Conference (SPEC), pp. 1–6, 2016



1 comments

SUHAIMI SELIMAN says:

Do electron charge in the substrate & charge trap has different characteris.

Why when apply higher gate voltage, electron charge in the charge trap flow opposite direction of the gate’s PHOTON ( + very charge ) as it is nearer to the gate

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