Signal Connectivity Checks Are Not Just For Design-For-Test Teams

By Pawini Mahajan and Raja Koneru

The complexity with system-on-chip (SoC) design continues to grow, creating greater complexity of the corresponding design-for-test (DFT) logic required for manufacturing tests. Design teams are challenged not only by high gate counts and the array of internally developed and third-party IP integrated into their designs: the need to achieve high-quality manufacturing tests of these complex designs has resulted in sophisticated DFT architectures that are challenging to verify. Unfortunately, when verification of the DFT logic points to a problem, debug can consume a lot of time. This is often the case for many DFT signals globally connected to many areas, such as test mode and scan enable signals. For these cases, DFT debug could be the equivalent of finding a needle in the haystack.  Fortunately, to address this need, advanced technology is available to ensure that the connection of DFT signals, or any other SoC signals, is correct and valid.

One common issue that impacts DFT engineers is correctly dealing with free-running clocks generated by phase-locked loops (PLLs). Automatic test pattern generation (ATPG) tools require control of clocks as well as other signals. To enable test pattern generation with PLLs, a specific DFT structure referred to as an on-chip clocking controller (OCC) is inserted by the DFT engineer. OCC is a mechanism that easily controls the PLL-generate clock and is accessible by the ATPG tool (see figure 1). In many finFET designs, it is typical for the output of the OCC to drive hundreds of cores and IPs. So, one verification challenge is to ensure these connections are correct. An additional challenge occurs when well-developed IP already contains an OCC. In those cases, the verification must also ensure that the top-level OCC is not driving the OCC of an IP (see figure 2).

Fig. 1: An OCC controller enables ATPG tools to control clocking.

Fig. 2: An OCC controller incorrectly driving a block-level OCC controller.

Another type of signal connectivity verification ensures that specific values and key signals are propagated as needed. Consider the case of a test mode signal to configure the design for manufacturing tests. Standard functional verification typically only determines if the test mode signal is off, not if the signal can be turned “on” (see figure 3).  This verification task is often left to DFT engineers.

Fig. 3: “Stuck-off” test mode of Block B not found with functional verification.

Signal connectivity verification technology, available in Synopsys TestMAX Advisor, can automate checking these and other related conditions. The technology enables usage at the RTL so issues can be identified and corrected early for maximum usefulness. Other valuable attributes of the technology include the ability to reuse checks across the design and provide a clear description of the root cause of the connectivity problem. While standalone signal connectivity checking is not replacing standard simulation-based verification, which could also find these issues, it is a complimentary ‘early warning’ verification.

The use of signal connectivity verification and checks is growing, especially as hierarchical DFT flows are adopted. Because of their usefulness, SoC designers responsible for full-chip integration are also deploying connectivity checks. Validating the connection of clocks and resets is a focused effort that finds issues much earlier (in the range of weeks) before the simulation phase. Integration of other components and pipeline stages can be done with high confidence that the signals are properly connected. With a supporting powerful description format or language, SoC integration can be made consistent and checked against defined methodologies using the connectivity rule language.

Connectivity checks were initially targeted for DFT teams. They were often responsible for top-level integration of DFT and needed to ensure many global and local test signal connections. As a result of the savings in verification effort, connectivity checks for DFT are taking off.  And now SoC design teams realize the advantages experienced by their DFT counterparts and are rapidly adopting connectivity checks.

Raja Koneru is an R&D engineer in the Hardware Analytics and Test Group at Synopsys, where he focuses on the development and implementation of full DFT design flow. He has a special interest in fault insertion and analysis on neural cache memories. He received a Master’s Degree in electrical and computer engineering from the University of Cincinnati in Ohio.