Stacking Logic On Logic

Advanced packaging can be an alphabet soup of possible approaches, from heterogenous integration of multiple die types into a single package, to three-dimensional stacking of multiple dies on top of each other. Three-dimensional chip stacking is most commonly seen in memory devices. Applied to logic, though, there are at least two different ways for integration to proceed.

Completely processed, passivated, and tested dies can be assembled into a stack. This is the method usually used for stacked memory modules. Stacking of finished chips reduces the footprint of the circuit and minimizes the risk of yield loss due to the stacking process itself. However, it provides relatively little performance improvement or design simplification.

Alternatively, once the first wafer has been processed as far as Metal 1, the fab can place a second wafer directly on top of it, fabricate a second transistor layer, and proceed through the back-end-of-line with the two wafers forming a single unit. This second approach, exemplified by CEA-LETI’s CoolCube technology, allows designers to treat the two dies as a single interconnected unit. It reduces interconnect delay and allows smarter partitioning of functions.

Unfortunately, it also introduces new problems. Copper interconnects are not welcome in a front end process due to the contamination risk. Processing of the second transistor layer must consider the thermal budget of the first layer. Thus, while the concept has been discussed for several years, actual demonstrations have been slow to appear.

So it was particularly noteworthy when, at this year’s VLSI conference, Laurent Brunet, a process integration engineer at CEA-LETI, and his colleagues, demonstrated successful CMOS over CMOS stacking in an industrial cleanroom-compatible process. First, they fabricated FD-SOI NMOS and PMOS transistors using a standard high temperature process with raised silicon source and drain junctions. After NiPt silicide contact formation and pre-metal dielectric deposition, CMP was used to planarize the whole structure. To facilitate connections between the first and second transistor tier, a short loop Metal 1 process followed, using tungsten fill rather than the more usual copper. Finally, direct bonding of an oxidized SOI wafer was used to transfer a 10 nm silicon layer for the second transistor tier. In the second tier, selective SiGe epitaxy formed raised source and drain junctions for both NMOS and PMOS, followed by activation by selective epitaxy regrowth.

The first layer required a maximum temperature of 1050°C, while the second one required temperatures up to 650°C. Though much cooler than a standard wafer process, this second layer still exceeds the 500°C limit imposed by the first layer. Low temperature epitaxy for the source and drain has been demonstrated, as have low-k spacers between the two wafers. These modifications have not yet been incorporated into the CoolCube process, though.

Because the first transistor tier imposes stringent thermal requirements, this kind of device stacking probably will have to overcome a performance penalty. Whether the design and interconnect delay advantages offer enough benefit to offset the disadvantages is likely to depend on the specific applications.

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