Stacking The Deck

By Matt Elmore
Can we finally say that 3D-IC design has emerged from the realm of theory and research to actual commercial implementation?

Xilinx recently announced initial shipments of its Virtex-7 H580T FPGA, described as “The world’s first 3D heterogeneous all programmable product.” The benefits of 3D implementation are many, as are its challenges. One of the hottest 3D-IC topics that companies are seeking solutions for is thermal integrity. Heat dissipation in an electronic system is a function of the chip’s power consumption; resistive loss in chip package/PCB interconnects, and heat-sinking devices placed on the PCB. In order to address the complexity of 3D-IC thermal integrity, analysis must consider the chip, package, and system (CPS) to provide an accurate solution.

Figure 1: Electron microscope image of a stacked 3D-IC design.

First, let’s discuss the benefits of 3D-IC design. 3D-IC provides increased bandwidth due to its ability to provide connections within a single package. These connections are shorter and are not limited by the high-energy loss found in traditional PCB interconnects. Power is significantly reduced as I/Os with reduced supplies and drive strengths are selected to drive smaller interconnect parasitics between chips. Form factor is reduced because we are utilizing the real estate of the z-axis. Finally, 3D-IC grants the ability to mix and optimize heterogeneous technologies (analog, digital, memory, etc.). As with most aspects of modern engineering, these benefits come with significant challenges.

Why is thermal such a huge issue for 3D-IC? Chips stacked in a 3D architecture are separated with silicon spacers that increase thermal resistance and add a low-k adhesive layer. Traditionally, heat dissipation is accomplished by external heat sinking, either through the bottom or the top of the package. The use of spacers reduces the ability of the package to direct heat to the sinks, so more heat is retained in the device.

Designers take advantage of the thermal conductivity of Through Silicon Vias (TSVs) to move heat through the z-axis. However, careful analysis is needed, considering the TSV’s ability to transfer heat and provide power. The floorplan architect must also take care not to align thermal hot spots between adjacent chips, as the heat transfer could compound in a thermal runaway scenario. To add to the challenge, the chips themselves generate more heat as we progress through technology nodes. The transistor leakage power increases while wires are shrinking and becoming more resistive, both resulting in more heat generation.

Figure 2: SRAM on top of logic chip, showing heat transfer through TSVs.

Increased temperature in an integrated circuit affects leakage, power integrity, reliability (EM) and stress. To see how temperature impacts these metrics, EDA providers must provide a solution that considers each aspect of the system including the chip, package, and PCB. It requires an accurate representation of the chip’s power response to temperature at micron resolution. This, in turn, needs to interact with die-package-board thermal and thermal-mechanical stress analysis—solving Fourier’s laws of conduction to converge on a power-thermal profile for each region of the chip and package.

A complete CPS thermal platform needs to consider each aspect of the system to provide quantitative feedback for designers to see the thermal impact on leakage, IR drop, EM and thermo-mechanical stress.

Figure 3: Thermal map. TSMC Reference Flow 12 test case. Memory and Logic on Silicon Interposer.

—Matt Elmore is a principal application engineer at Apache Design, a subsidiary of ANSYS.