How to improve test time for SoCs with multiple cores.
This white paper discusses various IEEE 1500 architectures that STMicroelectronics has deployed using the Synopsys DesignWare STAR Hierarchical System test solution. STAR Hierarchical System allows users to optimize test time on system-on-chips that use multiple cores. The white paper provides guidelines on interface IP wrapping with IEEE 1500 to improve test time. In addition, it discusses the STAR Hierarchical System architecture which enables test control capabilities of all fully integrated interface IP blocks that have IEEE 1500 wrappers. The white paper also discusses the process of wrapping and re-use of interface IP products.
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