tag: 14nm

New Challenges Emerge With FinFETs
By Ed Sperling - 05 Dec, 2013 - Comments: 0

Working at advanced process nodes is always tricky. There are new things to worry about and more rules to deal with initially, yet the promised benefit is improved performance, power and area, or cost. But at the next process node, and the one after that, there are so many variables coming into play that trying to make sense of the PPA equation is becoming much more difficult. Early reports ... » read more

Seven Ways To Improve PPA Before Moving To FinFETs
By Ed Sperling - 05 Dec, 2013 - Comments: 0

Henry Ford wrote in his autobiography, “Any customer can have a car painted any color that he wants so long as it is black.” And for decades, the semiconductor industry has marched to a similar theme set by Moore’s Law. But with the transition to finFETs harder than it first appeared, questions are beginning to pop up that is fueling a new level of confusion. While the growing list of... » read more

Leti Outlines FDSOI And Monolithic 3D IC Roadmaps
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

Semiconductor Engineering discussed the future roadmaps for fully depleted silicon-on-insulator (FDSOI) technology and monolithic 3D chips with Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti. SE: What are some of the technologies being developed at the Innovative Devices Laboratory? Vinet: The Innovative Devices Laboratory is involved with advanced CMOS. So basically... » read more

Paving The Way To 16/14nm
By Ed Sperling - 07 Nov, 2013 - Comments: 0

The move to the next stop on the Moore’s Law road map isn’t getting any less expensive or easier, but it is becoming more predictable. Tools and programs are being expanded to address physical effects such as electrostatic discharge (ESD), electromigration and thermal effects from increased current density. Any or all of these three checklist items can affect the reliability of a chip. A... » read more

The Week In Review: Oct. 18
By Mark LaPedus - 18 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling The problems continue with extreme ultraviolet (EUV) lithography. ASML promised to deliver an 80 Watt power source by year’s end. Now, the company said it only will have a 70 Watt source by mid-2014. “We are focusing on reaching the 70 Watts by the middle of next year,” said Peter Wennink, ASML’s CEO, in a conference call to discuss the company’s res... » read more

EDA Shows Continued Growth
By Ed Sperling - 16 Oct, 2013 - Comments: 0

EDA and IP revenue jumped 3.8% in Q2 to $1.65 billion, up from $1.59 billion in the same period in 2013, spurred by the need for new tools to design, create and verify SoCs using 16/14nm finFETs. Sequentially, the numbers reported by the EDA Consortium were down slightly from Q1, but the four-quarter moving average—considered a more reliable number because tools sales are long-term investm... » read more

Executive Briefing: Soitec CEO
By Mark LaPedus - 19 Sep, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss FD-SOI, solar and various technology trends with André-Jacques Auberton-Hervé, chairman and chief executive of Soitec, a supplier of silicon-on-insulator (SOI) substrates, solar concentrators and other products. SMD: The digital process roadmap is moving in several directions. Some pure-play foundries will offer ... » read more

Power Grid Analysis Heats Up At 20nm
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Do a simple Internet search for the term ‘power grid analysis’ and most of the results are academic sources. However, given the physics of either planar or finFET at 20nm and below, the power grid will see significant impacts. Overall, there are a number of technical implications of migrating from 28nm down to 20, 16 or 14 nm, with further impacts of moving fro... » read more

Experts At The Table: Challenges At 20nm
By Ed Sperling - 23 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. Wh... » read more

450mm: Out Of Sync
By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus The IC industry has been talking about it for ages, but vendors are finally coming to terms with a monumental shift in the business. The vast changes involve a pending and critical juncture, where the 450mm wafer size transition, new device architectures and other technologies will likely converge at or near the same time. In one possible scenario, 450mm fabs are projected ... » read more

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