Bulk CMOS Vs. FD-SOI

By Mark LaPedus - 19 May, 2016 - Comments: 2

The leading edge of the chip market increasingly is divided over whether to move to finFETs or whether to stay at 28nm using different materials and potentially even advanced packaging. Decisions about which approach to take frequently boil down to performance, power, form factor, cost, and the maturity of the individual technologies. All of those can vary by market, by vendor and by process... » read more

FinFET Scaling Reaches Thermal Limit

By Brian Bailey - 12 May, 2016 - Comments: 2

In 1974, Robert H. Dennard was working as an IBM researcher. He introduced the idea that MOSFETs would continue to work as voltage-controlled switches in conjunction with shrinking features, providing doping levels, the chip's geometry, and voltages are scaled along with those size reductions. This became known as Dennard's Law even though, just like Moore's Law, it was anything but a law. T... » read more

10nm Versus 7nm

By Mark LaPedus - 25 Apr, 2016 - Comments: 20

The silicon foundry business is heating up, as vendors continue to ramp their 16nm/14nm finFET processes. At the same time, they are racing each other to ship the next technologies on the roadmap—10nm and 7nm. But the landscape is complicated, with each vendor taking a different strategy. [getentity id="22865" e_name="Samsung"], for one, plans to ship its 10nm [getkc id="185" kc_name="fi... » read more

Insider’s Guide To Fab Technology

By Mark LaPedus - 21 Apr, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss fab technology with Matt Paggi, vice president of advanced technology development at GlobalFoundries. What follows are excerpts of that conversation. SE: What’s driving demand for semiconductors today? Paggi: You are aware of what the worldwide semiconductor revenue growth is this year. There are peaks and valleys in the worldwide semiconduc... » read more

Samsung Foundry’s Business Strategy

By Kelvin Low - 21 Apr, 2016 - Comments: 0

Wow! 2016 is off to a fast start. While visiting headquarters in Korea recently, I sat down with four members of Samsung Foundry’s global leadership team to discuss several key initiatives this year. Below are key excerpts from those conversations. Samsung Foundry’s Business Strategy Q: Can you expand on some of the macro business trends affecting the fabless/foundry industry? Jong S... » read more

Insider’s Guide To Photomasks

By Mark LaPedus - 17 Mar, 2016 - Comments: 1

Semiconductor Engineering sat down to talk about photomasks and lithography with Franklin Kalk, executive vice president of technology at Toppan Photomasks, a merchant photomask supplier. What follows are excerpts of that conversation. SE: What’s hot in mask technology these days? Kalk: It’s everything from the bleeding-edge like EUV to much more mature manufacturing. On the mature si... » read more

Will Directed Self-Assembly Pattern 14nm DRAM?

By Mattan Kamon - 17 Mar, 2016 - Comments: 1

Will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next-generation multi-patterning techniques to pattern the next memory and logic technologies? Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees. Nearly 75% believed DSA would insert into high-volume manufacturing within the next 5 years... » read more

The Big Shift

By Ed Sperling - 18 Feb, 2016 - Comments: 0

The number of chipmakers that truly can differentiate their products by moving to the next process node is falling, and that pool will continue to shrink even further over the next few years. Processor companies such as Intel and IBM always will benefit from scaling and architectural changes. So will GPU companies such as Nvidia, and FPGA vendors such as Xilinx, Microsemi and Altera (now par... » read more

Fallout From Scaling

By Ed Sperling - 03 Feb, 2016 - Comments: 0

By Ed Sperling & Ann Steffora Mutschler Semiconductor scaling is becoming much more difficult and expensive at each new node, creating sharp divisions about what path to take next for which markets and applications. What used to be confined to one or two clear choices is now turning into a menu of items and possibilities, often with no clear guarantees for a successful outcome. Views ... » read more

Behind The Intel-Altera Deal

By Ed Sperling - 31 Dec, 2015 - Comments: 3

Intel completed its $16.7 billion acquisition of Altera this week, wrapping up what is arguably the semiconductor industry's most important M&A transaction of 2015. Time and numbers will tell exactly how important. There are two big challenges to making this deal work. One involves a big shift in direction away from simply shrinking features to include new architectures and packaging approac... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?