Interconnect Challenges Grow

By Mark LaPedus - 20 Aug, 2015 - Comments: 1

It’s becoming apparent that traditional chip scaling is slowing down. The 16nm/14nm logic node took longer than expected to unfold. And the 10nm node and beyond could suffer the same fate. So what’s the main cause? It’s hard to pinpoint the problem, although many blame the issues on lithography. But what could eventually hold up the scaling train, and undo Moore’s Law, is arguably t... » read more

Tech Talk: 10nm Patterning

By Brian Bailey - 20 Aug, 2015 - Comments: 0

David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics, talks about triple and quadruple patterning after 20/16/14nm and what design teams need to understand to get this right. [youtube vid=7bjutPWakpw] » read more

Moving Electrons Is Getting Harder

By Ed Sperling - 13 Aug, 2015 - Comments: 1

Numerous executives across the ecosystem—from EDA and equipment companies to foundries—recently have stated that Moore's Law has at least 10 more years of life. This is interesting math, considering the semiconductor industry is now working on 10nm, with chips expected to roll out next year. So given that Moore's Law is on a two-year cadence of doubling the number of transistors every 24... » read more

Which Process, Material, IP?

By Ed Sperling - 30 Jul, 2015 - Comments: 1

For years chipmakers have been demanding more choices. They've finally gotten what they wished for—so many possibilities, in fact, that engineering teams of all types are having trouble wading through them. And to make matters worse, some choices now come with unexpected and often unwanted caveats. At the most advanced nodes it's a given that being able to shrink features and double patter... » read more

Inside Samsung’s Foundry Biz

By Mark LaPedus - 23 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about the foundry business, process technology, design and other topics with Hong Hao, senior vice president of the foundry business at [getentity id="22865" e_name="Samsung Semiconductor"]; and Kelvin Low, senior director of foundry marketing at Samsung Semiconductor. What follows are excerpts of that discussion. SE: The foundry business has alway... » read more

Tech Talk: Wafer Plane Analysis

By Ed Sperling - 23 Jul, 2015 - Comments: 0

Leo Pang, executive vice president at D2S, talks about the problems of patterning at 40nm and below and how to deal with them more effectively using existing equipment. [youtube vid=FbRyhw2q3fE] » read more

Power Breaks Everything

By Ed Sperling - 15 Jul, 2015 - Comments: 2

The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won't go away. In the past, most issues involving power—notably current leakage, physical effects such... » read more

Moore’s Law Reset?

By Ed Sperling - 13 Jul, 2015 - Comments: 0

GlobalFoundries today took the wraps off its 22nm FD-SOI process, promising to extend Moore's Law technologically without altering the economic equation—at least for the next couple of process nodes. Subramani Kengeri, vice president of global design solutions at [getentity id="22819" comment="GlobalFoundries"], said 22nm FD-SOI will provide the same 30% improvement in PPA that has been c... » read more

Here Comes 7nm

By Ed Sperling - 09 Jul, 2015 - Comments: 0

A consortium of companies involving IBM, GlobalFoundries and Samsung has rolled out the first 7nm test chip using silicon germanium as a substrate, using EUV to pattern multiple layers. While this doesn't mean the cost equation is even close to being solved, or that more than a handful of companies will push forward to that node anytime soon using SiGe as the substrate material, it does cre... » read more

IP Integration Challenges Increase

By Ed Sperling - 08 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

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Knowledge Centers
Entities, people and technologies explored

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3.5D: The Great Compromise

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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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