Is The Stacked Die Ecosystem Stagnating?

It is now widely agreed that not much has been happening in terms of adoption for 2.5D interposer and 3D ICs. “It seems like everyone is still at the starting line waiting for the race to begin," said Javier DeLaCruz, senior director of engineering of [getentity id="22242" e_name="eSilicon"]. "Interposer assembly and IP availability for effectively using the [getkc id="82" comment="2.5D IC... » read more

What’s Ahead For System-Level Design

By Ann Steffora Mutschler Architecting an SoC today is incredibly difficult. When you add in the number of available transistors, the manufacturing effects of smaller nodes, IP and software that must be integrated, among other things, the challenges just keep mounting. Depending on what market segment the SoC will be designed into has a huge impact, as well. “It is impossible to ove... » read more

Fundamentals For 3D IC Flows

While true 3D ICs are a few years off, 2.5D is here. There are some key differences, namely that with 2.5D the interposer is a passive die, but there also are some fundamental shared requirements. Samta Bansal, senior product marketing for Silicon Realization at Cadence asserted that first, the digital, custom and package environments must be seamless. “There has to be a co-design between ... » read more