tag: 2.5D

5/3nm Wars Begin
By Mark LaPedus - 23 Jan, 2020 - Comments: 6

Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond. The decision involves the move to extend today’s finFETs to 3nm, or to implement a new technology called gate-all-around FETs (GAA FETs) at 3nm or 2nm. An evolutionary step f... » read more

Making 3D Structures And Packages More Reliable
By Ed Sperling - 14 Jan, 2020 - Comments: 0

The move to smaller vertical structures and complex packaging schemes is straining existing testing approaches, particularly in heterogeneous combinations on a single chip and in multi-die packages. The complexity of these devices has exploded with the slowdown in scaling, as chipmakers turn to architectural solutions and new transistor structures rather than just relying on shrinking featur... » read more

What Worked, What Didn’t In 2019
By Brian Bailey - 19 Dec, 2019 - Comments: 1

2019 has been a tough year for semiconductor companies from a revenue standpoint, especially for memory companies. On the other hand, the EDA industry has seen another robust growth year. A significant portion of this disparity can be attributed to the number of emerging technology areas for semiconductors, none of which has reached volume production yet. Some markets continue to struggle, a... » read more

New Packaging Roadmap
By Katherine Derbyshire - 17 Dec, 2019 - Comments: 3

Historically, the electronics industry has drawn sharp distinctions between the integrated circuit chip, the package that protects it from the environment, and the board that connects it to other devices in a complete system. The circuit and systems worlds have been largely isolated from each other, using different tools, different processes, and different metrics for success. While integrated ... » read more

What’s Next For High Bandwidth Memory
By Mark LaPedus - 17 Dec, 2019 - Comments: 1

A surge in data is driving the need for new IC package types with more and faster memory in high-end systems. But there are a multitude of challenges on the memory, packaging and other fronts. In systems, for example, data moves back and forth between the processor and DRAM, which is the main memory for most chips. But at times this exchange causes latency and power consumption, sometimes re... » read more

Designing In 4D
By Ed Sperling - 26 Nov, 2019 - Comments: 0

The chip design world is no longer flat or static, and increasingly it's no longer standardized. Until 16/14nm, most design engineers viewed the world in two dimensions. Circuits were laid out along x and y axes, and everything was packed in between those two borders. The biggest problems were that nothing printed as neatly as the blueprint suggested, and current leaked out of two-dimension... » read more

Is There A Crossover Point For Mainstream Anymore?
By Ed Sperling - 21 Nov, 2019 - Comments: 0

Until 28nm, it was generally assumed that process nodes would go mainstream one or two generations after they were introduced. So by the time the leading edge chips for smartphones and servers were being developed at 16/14nm and 10/7nm, it was assumed that developing a chip at 28nm would be less expensive, less complex, and that the process rule deck would shrink. That worked for decades. Th... » read more

Planning For Panel-Level Fan-out
By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Migrating 3D Into The Mainstream
By Brian Bailey - 31 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for ANSYS' Semiconductor Business Unit; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Business;... » read more

What’s The Best Advanced Packaging Option?
By Mark LaPedus - 17 Oct, 2019 - Comments: 2

As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many advanced packaging options on the table already, and the list continues to grow. Moreover, each option has several tradeoffs and challenges, and all of them are still relatively expensive. ... » read more

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