New Packaging Roadmap

Heterogeneous Integration Roadmap addresses future packaging directions and gaps, simplifies definitions.

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Historically, the electronics industry has drawn sharp distinctions between the integrated circuit chip, the package that protects it from the environment, and the board that connects it to other devices in a complete system. The circuit and systems worlds have been largely isolated from each other, using different tools, different processes, and different metrics for success. While integrated circuit manufacturing is defined by a relentless focus on smaller feature sizes and more capable circuits, package and board manufacturers have had a single-minded focus on cost.

The recently released Heterogeneous Integration Roadmap makes it clear that the lines between domains are blurring. On-chip interconnects are becoming more dense. More complex circuits require more inputs and outputs, packed into a smaller area. Connections to the much larger circuit board features require increasingly complex intermediate layers within the package.

At the same time, mobile and Internet of Things devices are incorporating increasing numbers of sensors, RF devices, and passive components. Including as many of these elements as possible in a single package reduces the overall circuit footprint and, ultimately, the size of the finished device. Because analog devices generally do not benefit from scaling, as logic and memory elements do, heterogenous integration schemes use the optimal process technology for each component and then combine them in a single package.

These two factors have motivated an expanding array of packaging schemes. The Roadmap working groups saw clarifying the industry’s descriptive vocabulary as part of their mission. Observing that descriptions like “2.5D” have no consistent technical basis, they defined a new classification framework. In their scheme, “2D” architectures include all designs with two or more chips placed side by side. These architectures can be enhanced by additional wiring layers embedded in either an organic (“2DO”) or an inorganic (“2DS”) matrix. The “2D” classification thus includes packages with both resin-based redistribution layers and silicon or glass interposers. In this framework, the “3D” classification refers to architectures in which two or more devices are stacked vertically and interconnected without the agency of the package. Stacked dice connected by through-silicon vias (TSVs) or wire bonds fall into this category.

Three-dimensional architectures are attractive for both performance and cost reasons, offering both the smallest overall footprint and the shortest wiring distances between chips. Still, they have so far been limited to niche applications like image sensors and high density memories. System in package (SiP) advocates envision much more complex structures, but the Roadmap authors noted that the industry has yet to develop design tools, standards, or engineering expertise to support such a vision. How will the heat generated by high density logic dissipate without affecting the performance of thermal or optical sensors? Will the proximity of RF communications affect signal integrity within logic components or vice versa? Will the savings achieved with a reduced system footprint be enough to offset the costs of increased design and package complexity? The industry is only beginning to understand the design challenges that SiP approaches pose.

Two-dimensional architectures, in contrast, have sparked what the Roadmap authors called a “renaissance in packaging.” Products like the Integrated Fan Out (InFO) package from TSMC, first used with more than 1300 solderballs, demonstrated that high density fan-out packaging was feasible. This renaissance builds on a variety of so-called wafer-level package (WLP) architectures. The first WLP designs used redistribution layers to connect fine pitch bond pads on the periphery of the chip to the larger pitch solder bumps on the board. These “fan-in” designs brought peripheral bond pads toward the interior of the die, remaining within the chip’s original footprint.

With increasing interconnect density, it became necessary to “fan out” beyond the original chip’s footprint. Describing such designs as “wafer-level packaging” is potentially misleading. Individual dice are placed on a carrier wafer or panel with whatever spacing is needed to accommodate the redistribution structure. This “reconstituted wafer” is processed and encapsulated as a unit, then diced into individual packages, but the ultimate footprint of each package may be larger than that of the component dice.

In order to achieve more cost-effective throughput, manufacturers are considering panel processing techniques like those used in the solar cell and flat panel display industries. Even a modestly sized panel can accommodate as many as five times more packages as a 300 mm wafer. Here too, though, the Roadmap committee pointed out a lack of applicable standards for panel handling, materials, and processes. If chips are placed onto an organic matrix, what degree of flatness is required? If dice shift horizontally or vertically as the matrix expands or contracts during processing, how does their new position differ from the original position? Can subsequent processes adjust to compensate?

Many of the uncertainties discussed in the new Roadmap arise from the very nature of heterogenous integration. An IoT device with sensors, energy harvesting, and onboard energy storage is simply a different kind of component, requiring new approaches to design and reliability questions as well as to packaging. Like previous industry Roadmaps, this one is as much a catalog of looming obstacles as a pathfinding tool.



3 comments

Joseph Fjelstad says:

Thanks for posting this item

It is interesting how long some things take. We demonstrated fan-out wafer level packaging at Tessera 20 years ago because die shrink forced it. The microBGA technology we developed had originally fanned-in the I/O from fine pitch to a standardized course pitch that was compatible with standard SMT. To hold the foot pint standard, the I/O had to be created outside the die area. Fan-out wafer level packaging was the result. Finer pitches today for certain but the same basic concept.

Laurent says:

Regarding the development of panels, do you know if any major actor of the industry has already started working on it ?

Katherine Derbyshire says:

Chapter 23, Section 4.4 of the Roadmap looks at panel development. https://eps.ieee.org/images/files/HIR_2019/HIR1_ch23_WLP.pdf

Several of the big players have said they are working on it, drawing on existing technologies from the PCB, solar, and display sectors.

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