tag: 2.5D

2.5D Adds Test Challenges
By Jeff Dorsch - 06 Mar, 2017 - Comments: 0

OSATs and ATE vendors are making progress in determining what works and what doesn't in 2.5D packaging, expanding their knowledge base as this evolves into a mainstream technology. A [getkc id="82" kc_name="2.5D"] package generally includes an ASIC connected to a stack of memory chips—usually high-bandwidth memory—using an [getkc id="204" kc_name="interposer"] or some type of silicon bri... » read more

More Degrees Of Freedom
By Ed Sperling - 06 Feb, 2017 - Comments: 0

Ever since the publication of Gordon Moore's famous observation in 1965, the semiconductor industry has been laser-focused on shrinking devices to their practical, and more recently, impractical limit. Increasing transistor density has encountered a number of problems along the way, but it also has enabled us to put computers—which once filled specially built rooms—onto the desktop firs... » read more

Chip-Package-Board Issues Grow
By Ann Mutschler - 06 Feb, 2017 - Comments: 0

As systems migrate from a single die in a single package on a board, to multiple dies with multiple packaging options and multiple PCB form factors, it is becoming critical to move system planning, assembly, and optimization much earlier in the design-through-manufacturing flow. This is easier said than done. Multiple tools and operating systems are now used at each phase of the flow, partic... » read more

Betting On Wafer-Level Fan-Outs
By Ed Sperling - 06 Feb, 2017 - Comments: 2

Advanced packaging is starting to gain traction as a commercially viable business model rather than just one more possible option, propelled by the technical difficulties in routing signals at 10nm and 7nm and skyrocketing costs of device scaling on a single die. The inclusion of a [getkc id="202" kc_name="fan-out"] package for logic in Apple's iPhone 7, based on TSMC's Integrated Fan-Out (... » read more

Changing Direction In Chip Design
By Ed Sperling - 26 Jan, 2017 - Comments: 1

Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year's Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and ... » read more

What’s Next For Transistors
By Mark LaPedus - 23 Jan, 2017 - Comments: 1

The IC industry is moving in several different directions at once. The largest chipmakers continue to march down process nodes with chip scaling, while others are moving towards various advanced packaging schemes. On top of that, post-CMOS devices, neuromorphic chips and quantum computing are all in the works. Semiconductor Engineering sat down to discuss these technologies with Marie Semeri... » read more

Transferring Skills Getting Harder
By Ed Sperling - 19 Jan, 2017 - Comments: 0

Rising complexity in developing chips at advanced nodes, and an almost perpetual barrage of new engineering challenges at each new node, are making it more difficult for everyone involved to maintain consistent skill levels across a growing number of interrelated technologies. The result is that engineers are being forced to specialize, but when they work with other engineers with different ... » read more

Overcoming The Limits Of Scaling
By Ed Sperling - 29 Dec, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

What’s Missing In Advanced Packaging
By Ann Mutschler - 22 Dec, 2016 - Comments: 0

Even though Moore's Law is running out of steam, there is still a need to increase functional density. Increasingly, this is being done with heterogeneous integration at the package or module level. This is proving harder than it looks. At this point there are no standardized methodologies, and tools often are retrofitted versions of existing tools that don't take into account the challenges... » read more

Uncertainty Grows For 5nm, 3nm
By Mark LaPedus - 19 Dec, 2016 - Comments: 4

As several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner, R&D has begun for 5nm and beyond. In fact, some are already moving full speed ahead in the arena. [getentity id="22586" comment="TSMC"] recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion. The proposed fab is targeted to manufacture TSMC’s 5nm and 3nm processes, whic... » read more

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