tag: 2.5D

Preparing For 3D-ICs
By Ed Sperling - 16 Feb, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

More Manufacturing Issues, More Testing
By Ed Sperling - 08 Feb, 2022 - Comments: 0

Douglas Lefever, CEO of Advantest America, sat down with Semiconductor Engineering to talk about changes in test, the impact of advanced packaging, and business changes that are happening across the flow. What follows are excerpts of that discussion. SE: What are the big changes ahead in test? Lefever: It's less about inflection points and more like moving from algebra to calculus in the ... » read more

Next-Gen 3D Chip/Packaging Race Begins
By Mark LaPedus - 31 Jan, 2022 - Comments: 5

The first wave of chips is hitting the market using a technology called hybrid bonding, setting the stage for a new and competitive era of 3D-based chip products and advanced packages. AMD is the first vendor to unveil chips using copper hybrid bonding, an advanced die-stacking technology that enables next-generation 3D-like devices and packages. Hybrid bonding stacks and connects chips usin... » read more

A New Dimension Of Complexity For IC Design
By Ann Mutschler - 27 Jan, 2022 - Comments: 0

Full 3D designs involving logic-on-logic are still in the tire-kicking stage, but gaps in the tooling already are showing up. This is especially evident with static timing analysis (STA), which is used to validate a design’s timing performance by checking all possible paths for timing violations. STA issues began popping up particularly with the introduction of hybrid bonding, a bumpless p... » read more

Growth Spurred By Negatives
By Brian Bailey - 27 Jan, 2022 - Comments: 0

The success and health of the semiconductor industry is driven by the insatiable appetite for increasingly complex devices that impact every aspect of our lives. The number of design starts for the chips used in those devices drives the EDA industry. But at no point in history have there been as many market segments driving innovation as there are today. Moreover, there is no indication this... » read more

Future Challenges For Advanced Packaging
By Mark LaPedus - 20 Jan, 2022 - Comments: 1

Michael Kelly, vice president of advanced packaging development and integration at Amkor, sat down with Semiconductor Engineering to talk about advanced packaging and the challenges with the technology. What follows are excerpts of that discussion. SE: We’re in the midst of a huge semiconductor demand cycle. What’s driving that? Kelly: If you take a step back, our industry has always ... » read more

Setting Ground Rules For 3D-IC Designs
By Ed Sperling - 12 Jan, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Expanding Advanced Packaging Production In The U.S.
By Mark LaPedus - 05 Jan, 2022 - Comments: 0

The United States is taking the first steps toward bringing larger-scale IC packaging production capabilities back to the U.S. as supply chain concerns and trade tensions grow. The U.S. is among the leaders in developing packages, especially new and advanced forms of the technology that promise to shake up the semiconductor landscape. And while the U.S. has several packaging vendors, North A... » read more

Challenges With Stacking Memory On Logic
By Ed Sperling - 22 Dec, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Taking 2.5D/3DIC Physical Verification To The Next Level
By Siemens EDA - 21 Dec, 2021 - Comments: 0

As package designs evolve, so do verification requirements and challenges. Designers working on multi-die, multi-chiplet stacked configurations in 2.5/3D IC designs can use Calibre 3DSTACK physical verification checks to verify die alignments for proper connectivity and electrical behavior. The Calibre 3DSTACK precheck mode enables design teams to find and correct basic implementation mistakes ... » read more

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