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Unintended Coupling Issues Grow

More complex and increasingly heterogeneous designs, and multiple dies in a package, increase potential for unwanted interactions.

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The number of indirect and often unexpected ways in which one design element may be affected by another is growing, making it more difficult to ensure a chip — or multiple chips in a package — will perform reliably.

Long gone are the days when the only way that one part of a circuit could influence another was by an intended wire connecting them. As geometries get smaller, frequencies go up, voltages go down, and systems get larger, unintended couplings cannot be ignored. Failing to recognize all of these potential interactions, and to take action when needed, can lead to chip failures.

Analysis tools are becoming available for some of them, but there are few fully defined methodologies to tackle the problem in a holistic manner. So how many couplings do you need to be concerned about?

“There are predictable factors, and then there are unpredictable factors that influence the design process,” says Pradeep Thiagarajan, principal product manager for analog and mixed-signal IC verification solutions at Siemens EDA. “Typically, designers have a good handle on the predictable aspects that are accounted for within the design. Analysis ensures that their functional specifications can be met using the foundries’ certified models. But it’s the unpredictable ones, such as unintended couplings or noise, that can pose a daunting challenge. The key is it’s an invisible problem, and that’s what makes it scary.”

New packaging techniques are increasing the coupling mechanisms. “As electronic systems grow in complexity, so too do the nuances of achieving ‘right the first time’ by design,” says Sherry Hess, product marketing group director for system design and analysis technologies at Cadence. “Advancements in IC packaging technologies are an excellent example since several challenges impact 3D-IC design, not the least of which are the electromagnetic (EM) and thermal impacts associated with the interconnectivity between chiplets such as interposers.”

Signal and power integrity
Some of the couplings have been around for a while and are better understood. This includes signal integrity and power integrity. “Signal coupling is an increasing concern with the advanced process nodes,” says Siemens’ Thiagarajan. “These nodes promote and facilitate denser chip design with power, performance, and area as the main motives. However, the risk of signal coupling is now even more magnified. Signal coupling is a hidden problem. If it’s not detected quickly and accurately it can lead to catastrophic failures on the chip. You want to be predictive during the design verification process, not be reactive in discovering this in hardware.”

The issues are getting worse. “When you are routing signals inside of a chip, the wires are becoming skinnier and skinnier, but longer and longer, which makes them antennas,” says Mo Faisal, president and CEO of Movellus. “They are radiating whatever is going through them, and that is being radiated throughout the electromagnetic (EM) spectrum. Higher frequency means shorter wavelength. The shorter the wavelength, the higher the transmission effects, and then your digital signals are no longer digital signals. They become microwave signals, and you have to start worrying about termination and reflections. That requires a completely different kind of analysis. It basically requires microwave design to come into the package.”

The scope of the problem increases when there are multiple dies in a package. “As circuit density increases, the probability of EM interference grows,” says Cadence’s Hess. “It requires a complete simulation solution that can accurately predict the as-built performance. In a high-upfront-cost product like a 3D-IC, connecting simulation with design ensures accelerated time to market while managing costs and reducing uncertainty and risk.”

Power integrity also has been a concern for some time. “This requires a detailed analysis, certainly at the chip level,” says Shawn Carpenter, program director for 5G and space at Ansys. “You’ve got a couple billion gates, and many of them could switch at the same time. That will mess with another sub-block, and parts of your chip are going to mess with other parts of the chip. You could effectively modulate signals into other parts of your circuitry just because the power supply is being pulled up and down by these power integrity issues. If your chip contains radio transmitters, and its power supply is receiving some amount of modulation, or there’s some hash and noise on that supply, that gets into your final power amplifier and can become an intermodulation product in the final transmitted signal. That can cause your device to fail compliance testing.”

Power integrity continues to get worse. “In the future we will see more couplings through the power delivery network, especially in new nodes and/or stacked systems,” says Andy Heinig, group leader for advanced system integration and department head for efficient electronics at Fraunhofer IIS’ Engineering of Adaptive Systems Division. “In a centralized external power delivery network, block A can influence block B, with the noise resulting from the switching activities. The problem is increased by lower supply voltage, with less headroom and longer distances between the power supply and the transistors in stacked systems. To avoid such problems, more simulations — but also new architectures with more power regulators — can be used.”

Advanced packaging puts additional pressure on pin availability. “You’ve got power supply lines, each with their own dI/dt activity that are traversing all of these signals,” says Thiagarajan. “When we’re talking about smaller and denser chips, there’s an increasing power supply sharing that is happening between the different blocks inside the die. The main intent is to reduce your chip-level pin count, but in the process, these shared power supply grids and wires are now carriers of frequencies and dynamic transient events, as dictated by their own circuit loads. These now become influencers to any nearby signals.”

The power supplies themselves also are undergoing change. “There is new technology around wide bandgap semiconductors, using silicon carbide, gallium nitride, and gallium oxide,” says Steven Lee, product manager for power electronics design software at Keysight. “Because of this, power electronics is no longer operating in the tens of kilohertz. We’re probably beyond the hundreds of kilohertz in some designs. With higher switching speeds, capacitors get smaller, and inductors get smaller. But with these higher switching speeds, the inductors on the boards start becoming more of an issue with voltage spikes. While you can achieve the smaller sizes, the noise factor — the potential for noise — becomes much greater. You have to balance the pros and cons of this new technology. There is a learning curve with these wide bandgap technologies, and higher switching speeds bring along this really good set of smaller components. But at the same time, everybody’s seeing these issues with a higher level of radiated noise and voltage spikes as a result of parasitic inductance on the boards.”

Newer issues
There are some issues that are not as well understood or handled by tools. This includes thermal issues across multiple dies in a 3D system, for example, or problems caused by increasing frequency.

While digital frequencies have remained static for almost two decades, the same is not true for analog circuitry. “SerDes keeps pushing newer boundaries,” says Thiagarajan. “If you take the PCI or even DDR, these frequencies keep going up. Now you’ve got these frequencies flying all over the chip, and that adds more coupling issues to critical signals. There are analog signals, such as a VCOs, which control voltage, or a bandgap voltage, which is considered the stable reference voltage for many circuits. These are critical to the operation of the system. If those are influenced by these high frequency signals, the next thing you know is that you have an unstable PLL or a DLL and that could mess up the whole ecosystem within the chip.”

As more dies are placed in close proximity to each other, the issues become magnified. “Frequencies (and/or speeds) of operation are continuing to increase,” says Hess. “While quite small in terms of physical size, 3D-IC designs are actually very large from an electrical standpoint and thus very complex. To achieve first-pass success, designs require that the actual circuit layout be simulated in its entirety versus sliced and diced and magically reassembled.”

“It is essential to verify analog components against the actual use case as early and as accurately as possible,” says Benjamin Prautsch, group manager of advanced mixed-signal automation at Fraunhofer IIS’ Engineering of Adaptive Systems Division. “This includes, among others, digital trimming and/or control schemes, drifts in operating points and performance, switched load conditions, or feedback effects from one component to another or effects from packaging. Early modeling of these interaction among use case, analog components, and digital components is key in identifying unintended behavior early in the design process yielding better overview and less risk when designing the details.”

While in the past, it was common for digital circuits to have an adverse impact on analog, the issue has become bidirectional. “If there is any EM radiation coming off an analog wire that is being run at 16GHz or higher, it will be picked up by local digital circuits,” says Movellus’ Faisal. “Depending on the noise margin that you have, it may cause a problem. If you look at how digital designs are now closed, you do pretty hardcore reliability and EM simulations, and then you bring that into timing closure. Similarly for power integrity analysis, you bring that into timing closure to make sure your digital circuits will perform as designed.”

In addition, an increasing number of chips contain multiple radios, and their frequencies are going up as well. “Think about a mobile phone, where you probably have 14 different RF systems serving different bands,” says Ansys’ Carpenter. “You have GPS, several LTE bands, you’ve got near field communication on the low end, you’ve got potentially millimeter wave systems on the high end for these handsets. And you have to worry about all the stuff in that tight compact package. If interference gets into the receiver, it could defeat its ability to be able to receive signals intelligently. As frequencies go up, more things become effective antennas, and as we drive voltage levels further down, as we’re trying to reduce the power footprint of the electronics that are carrying the load for us, it’s a very slim margin. It’s a razor margin between communicating data effectively and getting bit error rates that go up to the point where you just clog everything up.”

Radio frequencies are adding complexity. “You used to be able to model passives very easily with some loss, or maybe something a little more complex, like an S parameter model,” says Ian Rippke, system simulation segment manager for Keysight. “But at 25GHz, 39GHz, commercial wireless frequencies, or automotive radar, up to 77GHz, or look at the emerging 6G environment pushing 100+ GHz, nothing is passive at those frequencies. Everything is finding ways to radiate and propagate. Whether it’s digital or an RF component, at some point the package stops looking like the traditional larger than a quarter wavelength, it starts having some real effects on the overall signal.”

Another coupling that is becoming more of an issue in 2.5D and 3D systems is thermal. “As designers decrease device sizes and integrate more components, thermal management is critical to ensure product longevity and reduce mean time between failures (MTBF),” says Hess. “The entire design must be simulated whole for its electrical viability, but also for its electrothermal viability.”

This may require a rethink in terms of modeling. “Thermal tends to be a lot lower frequency and requires simulation across a significant period of time,” says Faisal. “That’s where modeling comes in. When you start doing thermal analysis, you don’t worry about every single transistor. You just lump them into a few current sources, then run many smaller simulations.”

Activity dependency
What adds to the challenge is that many of these couplings are activity dependent. “What happens depends on what you’re doing with that unit,” says Carpenter. “That can vary the kinds of modulation you’re putting on your power rails, which are coupling onto signal buses, getting onto intermediate frequency chains, etc. To explore all of that, there is no way other than modeling and simulation.”

This will be significant challenge for chiplets, where the activity of neighboring devices is unknown. “You could have a base die that is packaged in different ways,” says Thiagarajan. “So now, although you may have one design, it may have a different set of PVT corners to characterize and validate to, compared to a different application. There could be the possibility of coupling that you see in a newer corner that was not prevalent in a prior application’s PVT corner. Maybe it happens on a circuit that has a low voltage headroom. Maybe in that second application, there’s even more high frequency signals that are flying around, or a certain clock that did not exist in the other application. Maybe there is a more power supply dI/dt switching happening in the other application and that can couple back into that signal.”

Planning for all of these possible interactions is essential. “In general, fast switching signals (referred to as aggressors) can induce unwanted disturbances into low activity signals (referred to as victims) due to capacitive/inductive coupling, which may degrade significantly the overall system-level performance,” says Francesco Settino, signal and power integrity engineer at Infineon. “Those problems may lead to a package re-design due to a specification violation issue detected too late during the development cycle. Therefore, the package design starts to play a key role in terms of cost and performance of the final product.”

This may require new modeling and analysis capabilities. “Co-existence modeling is something that could explore some of these issues, even as you’re putting the system block diagram together,” says Carpenter. “Will a particular set of blocks work well together? Will they interfere? Or is this design something we need to tweak and what can we understand from the failure in this proposed design? As we examine it with modeling and simulation, what insights can be gathered from it so that we can understand what to avoid or where can we build more margin?”

At all levels, it will require new models. “Modeling and model refinement of analog should be an integral part of both design and verification to quickly identify potential risks and solve problems early,” says Fraunhofer’s Prautsch. “Methods for rapidly modeling and/or model refinement, as well as improving interfaces of tools and design automation solutions across design domains and verification, are crucial activities to gain a broader view and, thus, better understand and diminish coupling effects.”

Parts of a workflow are coming together and getting tool support. “It’s a step by step, hierarchical process,” says Thiagarajan. “Once you have vetted out your block, you then need to think about the blocks it is probably going to talk with and understand the surrounding. Which signals between these boundaries can be affected due to proximity effects. It’s a brute force method and it’s not an easy method. You are trying to isolate, for particular stimuli, a critical path that needs to be analyzed. Then you change the stimuli to trigger a different functional mechanism, and that may influence a different output path that may affect other signals.”

These problems are being solved today using piecemeal approaches. “There’s no methodology you can buy or assemble to do this,” says Faisal. “That being said, big teams do have in-house methodologies for handling these things. People have stitched together their own methodology to do it. There is no holistic tool — one tool or subset of tools — that are readily stitched together to handle it. The person responsible for this is playing an air traffic control role to make sure all the pieces are playing nicely together and all the analyses are done. They may be done with many different tools. New EDA tools often come from chip designers, then they get absorbed by the EDA companies. This is exactly what’s happening here, too. The chip teams are coming up with ways of modeling it, ways to take care of it, and then slowly they will get incorporated into the systems.”

Tools for signal and power integrity do exist today, and these are being both extended and integrated into flows. Many of these solutions also tackle issues associated with appropriate abstractions.

Additional tools and flows are emerging. “Cadence offers a unified workflow that starts and stops with IC design, from a conceptual to manufacturing perspective, and includes both EM and ET analysis,” says Hess. “A streamlined advanced packaging solution offers the customer a model-what-you-make (MWYM) methodology that delivers a working design quickly, efficiently and reliably.”

Some of these tools are using novel analysis techniques. “Infineon has research work focused on the development of a methodology exploiting machine learning (ML) algorithms to enable optimized SoC-package co-design from the early stages of the development cycle,” says Frank Praemassing, senior principal engineer, mixed-signal architect for Infineon. “The main target is to detect potential specification violation issues at the system level that may occur due to signal integrity problems at the package level. Thus, it can provide guidelines for package design development and quick feedback to chip design development toward the optimization of the final chip-package design, saving development cost and time-to-market.”



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