Debug This! How To Simplify Coverage Analysis And Closure

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based on testbench stimulus. Today, functional verification is exponentially complex with the emergence of new layers of design requirements (beyond basic functionality) that did not exist years ago — f... » read more

Unintended Coupling Issues Grow

The number of indirect and often unexpected ways in which one design element may be affected by another is growing, making it more difficult to ensure a chip — or multiple chips in a package — will perform reliably. Long gone are the days when the only way that one part of a circuit could influence another was by an intended wire connecting them. As geometries get smaller, frequencies go... » read more

Finding The Bottom Of The Memory Trough

In announcing its Q2 fiscal 2019 results, Micron Technology, Inc. provided lower-than-expected revenue guidance of between $46 billion and $50 billion for the current quarter. However, what was particularly noteworthy was the company’s announcement to cut output by 5 percent due to weaker-than-expected market demand and its prediction that its customers’ inventory correction will last until... » read more

Emulation-Driven Implementation

Tech Talk: Haroon Chaudhri, director of Prime Power at Synopsys, talks about how to shorten time to market and increase confidence in advanced-node designs, while also reducing the amount of guard-banding and improving design freedom. » read more

Measuring And Analyzing SoC Performance With Verdi Performance Analyzer

SoC performance is a key competitive advantage in the marketplace. The choice and configuration of SoC components—protocol IP and interconnects, is geared towards maximizing overall SoC performance. A case in point is the use of HBM (High Bandwidth Memory) technology and controllers. Currently in its third generation, HBM boasts high-performance while using less power in a substantially small... » read more

Foundation IP For 7nm FinFETs: Design And Implementation

Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical challenges stemming from increasing variability associated with tighter pitches and more complex lithography steps. Design for variability and reliability considerations will require comprehensive model... » read more