How to identify the root causes of transaction bugs.
SoC performance is a key competitive advantage in the marketplace. The choice and configuration of SoC components—protocol IP and interconnects, is geared towards maximizing overall SoC performance. A case in point is the use of HBM (High Bandwidth Memory) technology and controllers. Currently in its third generation, HBM boasts high-performance while using less power in a substantially smaller form factor than DDR. It is a JEDEC-defined standard and is integrated with an SoC using a fine-pitch interposer. HBM’s low speed-per-pin and input/output capacitance reduce power consumption and increase power efficiency. In order to ensure that the HBM IP is tuned to achieve the desired performance-power balance, both performance and power consumption need to be measured. Measuring performance entails complex design calculations such as bandwidth/transfer rate per instance/channel, latency for different commands, page-hit/miss scenarios, etc. Protocol performance analysis and debug tools like Verdi Performance Analyzer can help designers easily visualize these important performance metrics, and also set min. and max. constraints on each metric and have the tool automatically identify violations of these constraints. Through direct integration with Verdi Protocol Analyzer, root cause of the offending transactions can be quickly identified.
To read more, click here.
Rising costs and gaps in equipment emerge as technology scales; new tools under development.
Explosion of data is forcing significant changes in where processing is done.
Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.
Researchers digging into ways around the von Neumann bottleneck.
Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.
Optimizing complex chips requires decisions about overall system architecture, and memory is a key variable.
Why data scrubbing and social issues could limit the speed of adoption and the usefulness of this technology.
Wally Rhines, Mentor’s CEO Emeritus, points to big shifts caused by AI, customization, uncertainty in the global economy and a changing customer base.
Smaller features and AI are creating system-level issues, but traditional ways of solving these problems don’t always work.
Agile development is gaining traction for developing hardware testbenches, but challenges remain.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
