tag: 28nm

Mix-And-Match Power Options
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler Choices abound today when it comes to considering a node shrink. Fully depleted silicon on insulator (FD-SOI) and finFET technologies along with other advanced transistor options are being evaluated, both together and independently of the other. It is possible to implement finFET on bulk 28nm CMOS or finFET on an FD-SOI process, for example. It is also possible to imp... » read more

To Shrink Or Not To Shrink…And How Much?
By Ed Sperling - 29 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler The 28nm semiconductor manufacturing node is in full swing with 20nm process development ramping quickly. As such, the industry has been looking ahead to the next node shrink to achieve the power, performance and cost advantages that a node shrink promises. However, as we are well aware by now, traditional CMOS planar technology is not scaling as it did in previous ge... » read more

Power Impacts On Advanced Node IP
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler With the move to the 28nm or 20nm process nodes, SoC engineering teams are seeing a significant amount of variations due to manufacturability. To reflect how a design element will be printed on the wafer, foundries offer many libraries with multiple corners for different voltages, timing and temperature, among other things. “At 28nm what we are seeing is a l... » read more

Wafer Leaders Extend Basis for Global SOI Supply
By Various Writers - 16 Oct, 2012 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation. SEH is a $12... » read more

ST’s FD-SOI Tech Available to All Through GF
By Various Writers - 08 Oct, 2012 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ In the spring of 2012, STMicroelectronics announced the company would be manufacturing ST-Ericsson’s next-generation (and very successful) NovaThor ARM-based smartphone/tablet processors using 28nm FD-SOI process technology. With first samples coming out this fall, ASN talks to Jean-Marc Chery, Executive Vice Pres... » read more

SPOTLIGHT ON FD-SOI, FINFETS AT IEEE SOI CONFERENCE
;1-4 OCT, NAPA
By Various Writers - 25 Sep, 2012 - Comments: 0

The 38th annual SOI Conference is coming right up. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications. Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the ... » read more

Mixed-Signal IP Design Challenges In 28nm Process And Beyond
By Various Writers - 23 Aug, 2012 - Comments: 0

As process technologies continue to scale aggressively, it is becoming more challenging when developing high-quality, high-speed mixed-signal IP. Specifically, the 28-nm process poses some unique challenges not found in 65-nm and 40-nm technology processes. This paper discusses the low power requirements found in 28-nm processes and addresses issues associated with the aggressive scaling of ... » read more

Designing into A Foundry Low-Power High-k Metal Gate 28nm CMOS Solution
By Various Writers - 31 Jul, 2012 - Comments: 0

28nm Super Low Power is the low power CMOS offering delivered on a bulk silicon substrate for mobile consumer and digital consumer applications. The 28nm process technology is slated to become the foundation for a new generation of portable electronics that are capable of handling streaming video, data, voice, social networking and mobile commerce applications. To view this white paper, clic... » read more

28, 20nm Nodes Demand Advanced Power Management
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler With the complexity of getting 28 and 20nm designs to reach desired yields with the desired power and performance on the shoulders of design teams, advanced power management techniques are a must. Sub-clock power gating, clock power gate structures, adaptive body bias and other techniques are making it possible. Sub-Clock Power Gating Far from a new techniqu... » read more

Experts At The Table: Pain Points
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: Where will the pain points be going forward? Kariat: 20nm is... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy