The Search For The Next Transistor

By Mark LaPedus - 20 Feb, 2014 - Comments: 3

In the near term, the leading-edge chip roadmap looks fairly clear. Chips based on today’s finFETs and planar fully depleted silicon-on-insulator (FDSOI) technologies are expected to scale down to the 10nm node. But then, the CMOS roadmap becomes foggy at 7nm and beyond. The industry has been exploring a number of next-generation transistor candidates, but suddenly, a few technologies are ... » read more

Can We Ever Agree On Moore’s Law?

By Ed Sperling - 13 Feb, 2014 - Comments: 0

Nearly five decades after Moore’s Law was first introduced—the famous observation turns 50 next year—we’re still debating it. There are disagreements about whether it was an economic or technology statement. There are questions about whether it was really every 24 months or every 18 months—it was actually both. And there are questions about which companies it really applied to and who... » read more

Heat Problems Grow With FinFETs, 3D-ICs

By Ann Mutschler - 13 Feb, 2014 - Comments: 2

From high-end consumer devices to rack-mounted arrays inside of data centers, thermal issues are becoming more serious—and getting much more attention. Driving this shift is the move from single chips to 3D ICs, whether they are interposer-based or stacked die. It’s a well-understood challenge: Die stacking can cause thermal issues because of the lack of a readily accessible thermal diss... » read more

The Road Ahead for 2014: Semiconductors

By Brian Bailey - 23 Jan, 2014 - Comments: 1

Last week, Semiconductor Engineering examined the 2014 predictions from several thought leaders in the industry and published those predictions that related to general market trends. Many of those predictions require some advances in semiconductor technologies and fabrications capabilities. It is those predictions that will be examined in this part, followed next week by the predictions related... » read more

Experts At The Table: What’s Next?

By Ed Sperling - 06 Jan, 2014 - Comments: 1

Semiconductor Engineering sat down with Sumit DasGupta, Si2; Simon Bloch, Samsung; Jim Hogan; Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: The future of technology isn’t just about technology. It’s about people and regulations, as well. Where are the hurdles ... » read more

The End Is Near

By Ed Sperling - 30 Dec, 2013 - Comments: 0

Looking back is easier than looking forward, and looking narrow is easier than looking wide. In 2013, there were several fundamental changes. Change No. 1: IP is now a lucrative market. From Synopsys’ standpoint, it’s been a lucrative market for some time. But the acquisitions made by Cadence, beginning in late 2012, coupled with the push by ARM into the micro-server market and the flail... » read more

Modern IC Packaging

By Various Writers - 18 Dec, 2013 - Comments: 0

Modern IC packaging technologies, such as 3D-IC, drive the need for IC, package and system co-design tools and methodologies. To download this white paper, click here. » read more

Different Economies Of Scale, And Lots Of Questions

By Ed Sperling - 12 Dec, 2013 - Comments: 0

Being able to shrink features and reach the next node is already an exclusive club. It will become more exclusive at 16/14nm, which is expected to hit volume production in 2015, and even more exclusive still at 10nm. In fact, it may begin to look like a semi-private affair. The argument being presented is that economies of scale will still exist for those companies with pockets deep enough ... » read more

3D-IC Requires Expanded Power Grid Analysis

By Christen Decoin - 05 Dec, 2013 - Comments: 0

At advanced nodes, effective power grid analysis is critical to ensure that the small dimension interconnects can handle current demands without introducing potential failure modes or signal integrity issues. Existing software tools for power analysis need to be extended and enhanced for 2.5D and 3D designs to fulfill new requirements and use models. This article describes some of the needed im... » read more

Thermally Challenged

By Brian Bailey - 05 Dec, 2013 - Comments: 0

Chips run hot and the thermal densities increase with every reduction in fabrication geometry. “When we go down to 16nm the local power density increases by 25% and the local gate density also increases by 25% to 30%,” explains Norman Chang, vice president of product strategy at Ansys/Apache. In fact, this is becoming such a large problem that it is affecting the scaling process itsel... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?