tag: 3D-IC

Fulfilling 3D-IC Trade-Off Analyses (And Benefits) With An AI Assist
By Pratyush Kamal - 13 Mar, 2025 - Comments: 0

As we walk around with supercomputers in our pockets and work at desks on even more powerful supercomputers, a lot of processing has moved to the cloud. As a politician described, this can be problematic on a day when there are no clouds in the sky. The world discovered the truth of those words when Crowdstrike struck on July 19, 2024. System designers who spent years balancing power, performan... » read more

3D-IC For The Masses
By Brian Bailey - 13 Mar, 2025 - Comments: 0

The concepts of 3D-IC and chiplets have the whole industry excited. It potentially marks the next stage in the evolution of the IP industry, but so far, technical difficulties and cost have curtailed its usage to just a handful of companies. Even within those, they do not appear to be seeing benefits from heterogeneous integration or reuse. Attempts to make this happen are not new. "A decade... » read more

What Exactly Is Multi-Physics?
By Brian Bailey - 13 Feb, 2025 - Comments: 1

Multi-physics is the new buzzword in semiconductor design and analysis, but the fuzziness of the term is a reflection of just how many new and existing problems need to be addressed simultaneously in the design flow with advanced nodes and packaging. This disaggregation of planar SoCs and the inclusion of more processing elements, memories, interconnects, and passives inside a package has cr... » read more

DFT At The Leading Edge
By Gregory Haley - 14 Jan, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the rapidly changing landscape of design for testability (DFT), focusing on the impact of advancements in fault models, high-speed interfaces, and lifecycle data analytics, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; D... » read more

What’s Next For Through-Silicon Vias
By Laura Peters - 06 Jan, 2025 - Comments: 0

From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Chiplet Interconnects Add Power And Signal Integrity Issues
By Adam Kovac - 12 Dec, 2024 - Comments: 0

The flexibility and scalability offered by chiplets make them an increasingly attractive choice over planar SoCs, but the rollout of increasingly heterogeneous assemblies adds a variety of new challenges around the processing and movement of data. Nearly all of the chiplets in use today were designed in-house by large systems companies and IDMs. Going forward, third-party chiplets will begin... » read more

ESD Verification For 2.5D And 3D-ICs
By Siemens EDA - 10 Dec, 2024 - Comments: 0

Ensuring your integrated circuit (IC) design can withstand electrostatic discharge (ESD) events without incurring damage or failure is an extremely important activity in IC circuit design and verification. While automated flows for ESD verification are well-established for regular 2D ICs, 2.5D and 3D integration presents new challenges in both ESD design and verification. The new automated ESD ... » read more

Efficient ESD Verification For 2.5/3D Automotive ICs
By Dina Medhat - 09 Dec, 2024 - Comments: 0

Protection against electrostatic discharge (ESD) events is an extremely important aspect of integrated circuit (IC) design and verification, particularly for 2.5/3D designs targeted for automotive systems. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical ... » read more

Critical Design Considerations For High-Bandwidth Chiplet Interconnects (TSMC)
By Technical Paper Link - 26 Nov, 2024 - Comments: 0

A new technical paper titled "High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions" was published by researchers at TSMC. Abstract: "The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by Artificial Intelligence a... » read more

Shift Left Is The Tip Of The Iceberg
By Brian Bailey - 14 Nov, 2024 - Comments: 1

Shift left is evolving from a buzzword into a much broader shift in design methodology and EDA tooling, and while it's still early innings there is widespread agreement that it will be transformative. The semiconductor industry has gone through many changes over the past few decades. Some are obvious, but others happen because of a convergence of multiple factors that require systemic change... » read more

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