The Challenge of 3D


Juan Rey, senior director of engineering for Mentor Graphics' Design To Silicon Division, talks about 3D stacking and 3D structures on chips. [youtube vid=YiH5IkxiEHU] » read more

‘What If’ In 3D


By Ed Sperling ‘What if’ questions have become standard across multiple pieces of the design chain for any SoC, but the number is multiplying at each new process node. When the industry begins moving to 2.5D and 3D over the next couple years, the number of tradeoffs will likely move from overwhelming to unmanageable. That will set in motion a number of efforts in semiconductor design. ... » read more

3D ICs: No Simple Answers


By Pallab Chatterjee Just how ready is the semiconductor industry for stacked die? That was the subject of a recent panel discussion involving ARM, Atrenta, Xilinx, Samsung and Mentor Graphics. The reasoning behind 3D stacking is becoming clearer at each node. I/O count and delay times are forcing different configurations, but the time frames for these changes and the gating constraints are... » read more

Memory, Bandwidth And SoC Performance


By Ann Steffora Mutschler High-end SoC architectures today can contain dozens of processing engines—multiple cores from MIPS and ARM, DSPs from Tensilica and CEVA, and even graphics processors. But with so many cores there also is a need for enormous amounts of memory, and that has been creating some unexpected design problems, In many cases so much memory is required for an SoC that some... » read more

Changes Ahead


With 3D stacked die looking increasingly promising, the question for much of the industry is exactly when this will happen, how it will happen, and what it will mean to the design process. To a large extent, in an attempt to buffer the risk, much of the fabless industry has been heading toward FPGA prototypes. It is uncertain whether that trend will continue at the same pace as 3D processes ... » read more

The Unifying Promise Of 3D


There’s been a lot of talk about 3D stacking lately. Mention it to any EDA vendor and they have plans in place. Mention it to large chipmakers and they’re already experimenting with it. And mention it to those several nodes behind and they’re ready to jump. Critics are quick to point out that all of these groups may not be talking about exactly the same thing. Slapping together two chi... » read more

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