tag: 3D stacking

Tech Talk: Graphic Headaches
By Ed Sperling - 24 Aug, 2011 - Comments: 0

Nvidia senior vice president of GPU engineering Jonah Alben talks with System-Level Design about the challenges of designing a graphics chip at advanced process nodes. [youtube vid=3Nc77aVH94g] » read more

Business First
By Ed Sperling - 19 Aug, 2011 - Comments: 0

The move to stacked die poses some interesting technology challenges and promises significant technology benefits, but the real driver is business—and for this market to work, it has to continue being about business. In the past it was technology first, business last. We are now at the stage where it is business first, technology last. Re-use of entire die as subystems, better use of desig... » read more

New Stacking Issues
By Norman Chang - 11 Aug, 2011 - Comments: 0

Reduced form factors, higher performance, and the demand for lower power necessitate the need for 3D-IC/silicon interposer designs with through-silicon vias (TSVs). That also creates major design challenges in three areas. The verification of power, signal, and reliability integrity—particularly with multi-stacked die on silicon interposer with TSVs—presents issues that can only be overcome... » read more

Customer Perspective: STMicroelectronics
By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling Philippe Magarshack, group vice president for technology R&D at STMicroelectronics, sat down with Low-Power Engineering to talk about some of the fundamental changes ahead in how SoCs are designed, built, how they perform and what steps can be taken to speed time to market. LPE: What do you see as the biggest changes ahead? Magarshack: One is the sheer size of the ecosy... » read more

Bigger Pipes, New Priorities
By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Ann Steffora Mutschler From the impact of stacking on memory subsystems to advances in computing architecture, Micron Technology is at the forefront in the memory industry. System-Level Design sat down to discuss challenges, as well as some possible solutions, that plague memory subsystem architects with Scott Graham, general manager for Micron’s Hybrid Memory Cube (HMC) and Joe Jeddeloh,... » read more

Stacks And Stacks
By Ed Sperling - 28 Jul, 2011 - Comments: 0

Talking about stacked die is sort of like describing Africa as a country. First of all, it’s wrong—despite some politicians’ statements to the contrary. And second, lumping everything together under a single heading probably adds more confusion than clarity. There are several ways to approach this semantics problem. One is by function. Memory on memory, memory on logic, and logic on l... » read more

Experts At The Table: Multi-Foundry Strategies
By Ed Sperling - 26 Jul, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; John Murphy, director of strategic alliances marketing at Cadence; Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics; Bob Smith, vice president of marketing and business development at Magma, and Linh Hong, vice president ... » read more

Not So Fast
By Ed Sperling - 01 Jul, 2011 - Comments: 0

Semiconductor engineering has always been about taking two steps forward and one step back. Or, if you’re more cynical, you don’t really move at all. You just get better at what you do. The cynical approach is that nothing is really new because it’s all been done before. In effect, 2.5D packages are multi-chip modules with a better business case and more advanced versions of what exist... » read more

Tech Talk: Atrenta CTO
By Ed Sperling - 06 Jun, 2011 - Comments: 0

Bernard Murphy talks with System-Level Design about what's changing in the semiconductor design area, how 3D stacking will affect design and what's needed in EDA tools. [youtube vid=kT3vs4sldSk] » read more

One-On-One: Aart de Geus
By Ed Sperling - 01 Jun, 2011 - Comments: 0

Synopsys' CEO talks with Low-Power Engineering about the future of EDA, the changes in IP, stacked die and 20nm designs. [youtube vid=x9TKRC48OG0] » read more

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