tag: 3nm

Advancing To The 3nm Node And Beyond: Technology, Challenges And Solutions
By Michael Hargrove - 19 Aug, 2021 - Comments: 0

It seems like yesterday that finFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of finFETs began at the 22nm node and has continued through the 7nm node. Beyond 7nm, it looks like nanosheet device structures will be used for at least the 5nm and probably the 3nm nodes. The nanosheet device structure is the brainc... » read more

Current And Future Packaging Trends
By Mark LaPedus - 19 Aug, 2021 - Comments: 1

Semiconductor Engineering sat down to discuss IC packaging technology trends and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Thomas Uhrmann, directo... » read more

Impact Of GAA Transistors At 3/2nm
By Brian Bailey - 16 Aug, 2021 - Comments: 2

The chip industry is poised for another change in transistor structure as gate-all-around (GAA) FETs replace finFETs at 3nm and below, creating a new set of challenges for design teams that will need to be fully understood and addressed. GAA FETs are considered an evolutionary step from finFETs, but the impact on design flows and tools is still expected to be significant. GAA FETs will offer... » read more

The Increasingly Uneven Race To 3nm/2nm
By Mark LaPedus and Ed Sperling - 24 May, 2021 - Comments: 2

Several chipmakers and fabless design houses are racing against each other to develop processes and chips at the next logic nodes in 3nm and 2nm, but putting these technologies into mass production is proving both expensive and difficult. It's also beginning to raise questions about just how quickly those new nodes will be needed and why. Migrating to the next nodes does boost performance an... » read more

What’s Next In Fab Tool Technologies?
By Mark LaPedus - 12 May, 2021 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography and other next-generation fab technologies with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fuj... » read more

Foundry Wars Begin
By Mark LaPedus - 19 Apr, 2021 - Comments: 3

Leading-edge foundry vendors are gearing up for a new, high-stakes spending and technology race, setting the stage for a possible shakeup across the semiconductor manufacturing landscape. In March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Intel announced plans to build ... » read more

Changing The Rules For Chip Scaling
By Ed Sperling - 10 Mar, 2021 - Comments: 0

Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about the incessant drive for chip density, how to improve that density through other means than just scaling, and why this is so important for the chip industry. » read more

New Transistor Structures At 3nm/2nm
By Mark LaPedus - 25 Jan, 2021 - Comments: 12

Several foundries continue to develop new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production is going to be difficult and expensive. Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s finFET transistors to new gate-all-around field-effect trans... » read more

Variation Threat In Advanced Nodes, Packages Grows
By Ed Sperling - 21 Dec, 2020 - Comments: 0

Variation is becoming a much bigger and more complex problem for chipmakers as they push to the next process nodes or into increasingly dense advanced packages, raising concerns about the functionality and reliability of individual devices, and even entire systems. In the past, almost all concerns about variation focused on the manufacturing process. What printed on a piece of silicon didn't... » read more

AI And High-NA EUV At 3/2/1nm
By Mark LaPedus - 16 Dec, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

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