The Week In Review: System-Level Design

By Ed Sperling - 14 Feb, 2014 - Comments: 0

Cadence bought TranSwitch’s high-speed interface IP assets. TranSwitch, which made chips for communications equipment, filed for bankruptcy in November. (The company’s Web site is no longer active.) Cadence also won a deal with Microsoft, which will use Tensilica processors in the new Xbox One audio subsystem. And Cadence rolled out HiFi Audio Tunneling for Android, which takes advantage of... » read more

What Can Go Wrong?

By Kurt Shuler - 25 Sep, 2013 - Comments: 0

It’s no surprise that most corporate system-on-chip (SoC) design teams are dispersed throughout the world, with different functional teams often located in different countries and continents. For example, we have many customers whose SoC architecture is defined in the United States, but subsystems such as graphics and signal processing are designed elsewhere. Companies choose this approach in... » read more

Drowning In Data

By Ed Sperling - 13 Jun, 2013 - Comments: 0

By Ed Sperling The old adage, “Be careful what you wish for,” has hit the SoC design market like a 100-year storm. After years of demanding more data to understand what’s going on in a design, engineering teams now have so much data that they’re drowning in it. This is most obvious at advanced process nodes, of course. But it’s also true these days at more mainstream nodes such as... » read more

The Rise Of Layout-Dependent Effects

By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Designing for today’s advanced semiconductor manufacturing process nodes brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Layout-dependent effects (LDE), which emerged at 40nm and are having a larger impact at 28 and 20nm, introduce variability to circuit ... » read more

Leveraging The Past

By Ed Sperling - 28 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler It’s easy to forget that not every design today is targeted at 20nm, given the amount of focus put on the bleeding edge of technology. But in fact a large number of designs utilize the stability and reliability of older manufacturing nodes, as well as lower mask costs, by incorporating new design and verification techniques, with 2.5D designs being a prime example. ... » read more

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tag: 40nm

The Week In Review: System-Level Design

What Can Go Wrong?

Drowning In Data

The Rise Of Layout-Dependent Effects

Leveraging The Past