CEO Outlook: It Gets Much Harder From Here

By Ed Sperling - 03 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

The Next Materials Race

By Ed Sperling - 05 Nov, 2018 - Comments: 0

Trade wars are costly on many fronts, and a trade war between the United States and China is bound to cause a variety of problems that no one anticipated. But in some areas, there may be a silver lining. And where there is no silver lining available, other materials may suffice. For decades, big chipmakers have been squeezing the entire semiconductor supply chain in a race to double the num... » read more

The Big Blur

By Ed Sperling - 20 Sep, 2018 - Comments: 0

Chip companies, research houses, foundries—and more recently large systems companies—have been developing alternative technologies to continue scaling power and performance. It's still not obvious which of those will win, let alone survive, or what they will do to the economics of developing chips. For more than five decades, the biggest concern was scaling devices in order to save money... » read more

Cheaper Fan-Outs Ahead

By Mark LaPedus - 07 Aug, 2017 - Comments: 6

Packaging houses continue to ramp up fan-out wafer-level packages in the market, but customers want lower cost fan-out products for a broader range of applications, such as consumer, RF and smartphones. So in R&D, the industry for some time has been developing next-generation fan-out using a panel-level format, a technology that could potentially lower the cost of fan-out. But there are ... » read more

450mm And Other Emergency Measures

By Ed Sperling - 22 Sep, 2016 - Comments: 0

Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months. Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling. Whether either of these approach... » read more

Changing Economics In Chip Manufacturing

By Ed Sperling - 18 Aug, 2016 - Comments: 1

The foundry and equipment businesses are poised for significant changes that could affect the balance of power far beyond just the semiconductor manufacturing sector. It’s no secret that the number of companies developing new chips at 7nm is shrinking. There will be even fewer at 5nm. The business case for moving forward is that density must provide a competitive edge. But that density imp... » read more

The Road To 5nm

By Ed Sperling - 23 Jun, 2016 - Comments: 1

There is strong likelihood that enough companies will move to 7nm to warrant the investment. How many will move forward to 5nm is far less certain. Part of the reason for this uncertainty is big-company consolidation. There are simply fewer customers left who can afford to build chips at the most advanced nodes. Intel bought Altera. Avago bought Broadcom. NXP bought Freescale. GlobalFoundrie... » read more

Behind The Intel-Altera Deal

By Ed Sperling - 31 Dec, 2015 - Comments: 3

Intel completed its $16.7 billion acquisition of Altera this week, wrapping up what is arguably the semiconductor industry's most important M&A transaction of 2015. Time and numbers will tell exactly how important. There are two big challenges to making this deal work. One involves a big shift in direction away from simply shrinking features to include new architectures and packaging approac... » read more

Increasing Challenges At Advanced Nodes

By Ed Sperling - 22 Oct, 2015 - Comments: 1

Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation. SE: Where do you see problems at future nodes? Patton: At the device level, we have to be able to pattern these thing... » read more

Analysis: Applied-TEL Scrap Merger

By Mark LaPedus - 27 Apr, 2015 - Comments: 0

After several delays due to a myriad of complex regulatory issues, Applied Materials’ proposed deal to buy Tokyo Electron Ltd. (TEL) has been scrapped. It appears that the U.S. Department of Justice (DoJ) stepped in and blocked the deal. Now that the deal has been terminated, Applied Materials and TEL are separately re-grouping, and are back to where they originally started as fierce compe... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?