Unraveling The Mysteries At IEDM

By Mark LaPedus - 19 Dec, 2014 - Comments: 0

In some respects, the 2014 IEEE International Electron Devices Meeting (IEDM) was no different than past events. The event, held this week in San Francisco, included the usual and dizzying array of tutorials, sessions, papers and panels. On the leading-edge CMOS front, for example, the topics included [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D IC"] chips, III-V materials, [getkc ... » read more

And the Winner is…

By Brian Bailey - 18 Dec, 2014 - Comments: 0

Semiconductor Engineering now has its first full year under its belt, and I have to say it has been an incredible year. Not only did we exceed a million page views in our first year, but we also got started on the Knowledge Center, an endeavor the likes of which has never been attempted in our industry. It is still very young and has a lot of growing up to do, but it is a wonderful start. We wo... » read more

This Is What 450mm Wafers Look Like

By SEMI - 14 Aug, 2014 - Comments: 0

The first fully patterned 450mm wafers were on display at SEMICON West 2014 in South Hall and also showcased in the 450mm Technology Development Session. Fully patterned 450mm wafers produced using Molecular Imprints’ Imprio nanoimprint lithography (NIL) tool have been shown before (including at SEMI ISS meeting in January 2013). However, the 450mm wafers on display at SEMICON West were produ... » read more

EUV Is Key To 450mm Wafers

By Katherine Derbyshire - 31 Jul, 2014 - Comments: 1

Whether the wafers in question are 200 mm in diameter, or 300 mm, or potentially 450 mm, larger wafer sizes have always been justified by manufacturing economics. If the cost to process a wafer stays the same, but the wafer contains more devices, then the cost per device goes down. For processes that apply to the entire wafer at once — etch, deposition, cleaning, and so forth — the equation... » read more

Confusion Does Not Equal Paralysis

By Ed Sperling - 10 Jul, 2014 - Comments: 0

After attending the two biggest semiconductor conferences in the world, along with a long list of notable conferences targeted to a wide variety of technologies and engineering disciplines, it’s clear the industry is racing ahead. But “ahead” is now a relative term. While Moore’s Law satisfied both economic and technological requirements, it was easy to figure out what “ahead” me... » read more

Has The IC Industry Hit A ‘Red Brick Wall’?

By Mark LaPedus - 19 Jun, 2014 - Comments: 2

In the mid-1980s, the semiconductor industry was in a crisis. Chipmakers were looking for ways to break the magical one-micron barrier. Many thought X-ray lithography would be required to break the barrier, but as it turned out, traditional optical technology did the trick. And the industry marched on. Then, in 2000 or so, the IC industry was nearing the so-called “red brick wall,” which... » read more

Is 450mm Dead In The Water?

By Mark LaPedus - 15 May, 2014 - Comments: 3

At one time, Intel, TSMC and Samsung were aggressively beating the 450mm drum. Chipmakers wanted, if not demanded, 450mm pilot line fabs by 2016, with high-volume manufacturing 450mm plants slated by 2018. At least for those companies, 450mm made some sense. Moving to 450mm wafers would supposedly give chipmakers a 2.25x boost in wafer area and a 30% cost reduction over 300mm substrates. But... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 18 Apr, 2014 - Comments: 0

There is more evidence of a fab tool slowdown. In fact, ASML itself sounded the alarm during its earnings conference call this week. “ASML noted uncertainty regarding the timing of both the 16/14 nm finFET ramp at foundries (the company is seeing a delay from customers as the technology is still in development, in our view) and 3D NAND,” said Weston Twigg, an analyst from Pacific Crest Secu... » read more

Searching For Rare Earths

By Mark LaPedus - 17 Apr, 2014 - Comments: 2

The semiconductor industry is pre-occupied with several and expensive technologies at once. One the device side, the industry is looking at new chip architectures, such as 3D NAND, finFETs and stacked die. On the manufacturing front, there is 450mm technology, next-generation lithography (NGL) and new materials. And that’s just the tip of the iceberg. Another technology that deserve... » read more

Favorite Forecast Fallacies

By Barry Pangrle - 14 Apr, 2014 - Comments: 0

It’s difficult to make predictions, especially about the future. – An Old Danish Proverb. The GSA Silicon Summit was held on Thursday, April 10th at the Computer History Museum in Mountain View, CA. The opening panel session was entitled Advancements in Nanoscale Processing. The panelists were Rob Aitken (ARM), Adam Brand (Applied Materials), Peter Huang (TSMC), Nick Kepler (VLSI Researc... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?