Has The IC Industry Hit A ‘Red Brick Wall’?

Imec CEO Luc Van den hove warns that the IC industry is approaching the limit in chip scaling. What does that really mean?


In the mid-1980s, the semiconductor industry was in a crisis. Chipmakers were looking for ways to break the magical one-micron barrier. Many thought X-ray lithography would be required to break the barrier, but as it turned out, traditional optical technology did the trick. And the industry marched on.

Then, in 2000 or so, the IC industry was nearing the so-called “red brick wall,” which was a figurative way to describe the various technical barriers that could halt chip scaling. At that time, the industry was looking to find new solutions for the gate stack, interconnects, low-k dielectrics, among others.

Also at the time, some chip experts claimed that planar transistors could not be scaled below 50nm. As a result, there was a belief that the industry required a new transistor architecture, such as finFETs, SOI-based devices and vertical structures.

Eventually, the industry found solutions to the tough problems, thanks to the advent of dual-damascene copper interconnects and high-k/metal-gate. And with optical lithography, the industry scaled the transistor beyond 50nm.

Meanwhile, at a recent event, Luc Van den hove, president and chief executive of Imec, warned that today’s IC industry is once again approaching the “red brick wall” in chip scaling. “We are in the same situation as we were 15 years ago,” Van den hove said in an interview. “Some people are getting worried if we can continue this. Because of multiple patterning, and the fact that EUV is delayed, there is a worry. Are we going to be able to afford this next-generation technology?”

Does this all sound familiar? Once again, there seems to be a crisis in lithography and interconnects, among other areas. Down the road, the industry will likely require a next-generation transistor with new and faster channel materials.

Near term, the industry also faces other challenges. Citing the shift towards more complex chip structures, materials and multiple patterning, IC manufacturing costs are now increasing 20% to 30% per node starting at the 20nm/16nm/14nm foundry node, as opposed to 5% to 15% in prior nodes, according to Pacific Crest Securities.

Chipmakers are expected to ramp up finFETs and 3D NAND, but they are showing a “great restraint with respect to spending plans, limiting the rate of new node transitions and overall capex upside,” according to Pacific Crest Securities.

In other words, the technology and node transitions are slowing. And in another ominous sign for fab tool vendors, there are fewer chipmakers that can afford to play at the leading edge. In fact, Intel, Samsung and TSMC will account for about 55% of the industry’s capital spending this year, according to Pacific Crest.

In any case, what are the short- and long-term prospects for the industry? And can the industry break through the “red brick wall” and do it economically?

Earlier this year, Semiconductor Engineering caught up with Imec’s Van den hove to get his reading on the state of the industry, including 450mm technology, EUV, next-generation transistors and other subjects.

But since earlier this year, the industry has undergone some dramatic changes. At a recent event in June, Semiconductor Engineering once again sat down with Van den hove to get an update on the industry. Here’s excepts of that conversion:

SE: Is chip scaling over?

Van de hove: Some people are maybe somewhat worried about the future of our industry. But I think there are loads of opportunities. You have to think outside the classical boarders. So the question is not whether scaling will go on. The question is whether it will slow down.

SE: So the industry has not hit the “red brick wall”?

Van de hove: This is just the same situation as 15 years ago. We will just have to solve some of these technical challenges. For example, I am convinced EUV will be there in one or two years. At the same time, we will have the demands from the applications. So, we will create a whole new momentum in the industry, or continue that momentum.

SE: What about the economics and the cost of IC scaling?

Van de hove: It is a challenge. There was a good and recent presentation on this from (Synopsys Chairman and co-CEO) Aart de Geus. It was good in the sense that maybe we will have to accept a little bit higher cost for these advanced nodes. If you look at the total value chain, there is enough money. Maybe it has to be re-distributed a little bit more. But if there is a sufficient demand for the technology, people may want to pay for an extra premium in some cases. Having said that, there is still a need to push on cost.

SE: What’s the status of EUV?

Van de hove: Over the last two quarters, a lot of progress has been made. The progress is there (with EUV and the power source). I think it’s on the order of 35 wafers per hour now. So for 7nm, I am pretty confident EUV will be there at that time.

SE: Is directed self-assembly (DSA) making any progress?

Van de hove: We are strong believers in DSA. There are still issues with DSA, such as defectivity, but we’ve seen progress. We will see a gradual insertion for DSA. We may see some at 10nm. In our research, we are targeting 7nm.

SE: What’s the progress of III-V materials for use in high-mobility channels at 7nm and 5nm?

Van de hove: III-V materials for finFETs will come, but it’s not an easy one. On the other hand, we are making a lot of progress with germanium. It’s clearly the intermediate step. Whether that will work well enough for the n channel is still to be seen. But for the p channel, that is certainly a very good alternative. For n channel, we could use germanium or III-V. It will really depend on the progress we make on defectivity with III-V. But I wouldn’t be surprised if we can’t do germanium at 7nm.

SE: Traditionally, Imec has been developing next-generation technologies based on bulk CMOS. One of your CMOS partners is Samsung. Samsung is suddenly interested in fully depleted silicon-on-insulator (FDSOI). Is Imec interested in pursuing FDSOI or next-generation SOI on finFET technologies?

Van de hove: We’ve collaborated with Soitec for quite some time. We’ve done work on FDSOI in the past. 28nm is a node where you will see a lot of volume. It’s a node that will have a long life time. FDSOI can be an interesting option for these ultra-low power versions of 28nm. We are also looking into SOI to scale the finFET at 10nm or sub-10nm. Those are all options we are investigating. So, it’s not a matter of SOI versus not SOI. At the end of the day, what’s the difference between the gate-all-around device you build on an SOI substrate or build on a bulk substrate? The question is how you can build it most effectively. Those are the scenarios we are investigating.

SE: For years, Imec has been working on silicon photonics. In recent presentations, Imec has been talking about stacking a silicon photonics die with other dies, such as memory and logic. Where do you see that going?

Van de hove: We’ve combined our expertise in photonics with the 3D group. We can use the interposer technology as a substrate for integrated photonics components. Now, we are at a tipping point for silicon photonics in terms of cost versus performance. We will see (a stacked silicon photonics solution) first in high performance computing type of applications in the data center. It will ripple down to other applications.

SE: Imec has been talking about building a 450mm extension at its current 300mm R&D fab site. What’s the status?

Van de hove: We are building the fab. It’s completely compatible with 450mm. But it’s no secret that the 450mm transition has been delayed. Still, we started with the construction of our facility. In fact, it started a few weeks ago. So we will start using the facility for 300mm tools. As soon as 450mm takes off, we can start putting 450mm tools in there.


[…] Editor Mark LaPedus investigates—and asks some important questions—about whether the IC industry has hit a “red […]

Daniel Dobkin says:

Power scaling ended in 2007, as you can tell by the fact that clock speeds have been stagnant since. Moore’s law worked because cost per transistor was falling; that ended at the 28nm node. If you attended packaging conferences in 2015/2016 you know that the huge sudden trend was the use of packages incorporating multiple chips with either a silicon-based or plastic-based high density interconnect. This is done because it’s too expensive to put a circuit on the most advanced nodes. This tells us that chip scaling is done economically even if it isn’t done technologically, and that the era of system-on-chip has ended, to be replaced by system-in-package. Every technology has an S-curve, and when it is going up everyone thinks it will go up forever, but the steam engine of 1900 worked only slightly better than the one from 1880. Eventually silicon IC’s will be replaced, but this can only happen when there is a profitable path from the beginnings of a new technology to the moment where it can take over. That requires lots and lots of infrastructure and takes a long time.

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