Executive Insight: Luc Van den hove

Imec’s CEO talks about process technology, EUV, new gate structures, and what technology will look like over the next few nodes.


Semiconductor Engineering sat down to discuss current and future process technology challenges with Luc Van den hove, president and chief executive of Imec. What follows are excerpts of that conversation.

SE: The industry is simultaneously working on several new and expensive technologies. This includes extreme ultraviolet (EUV) lithography and the next-generation 450mm wafer size. The industry is also working on new chip architectures and materials. What are the basic timelines for these technologies? And can the industry make it happen in spite of the R&D costs?

Van den hove: Nothing is easy in this industry anymore. It is going to be complicated. And I am not saying that everything will all happen at the same time. As I have mentioned before, at the 7nm node, we will see the first-generation of high-mobility materials. And if 450mm stays on the timeline, we could see the introduction of 450mm in the 2018 or 2019 timeframe. But long before that, we will have to resolve the EUV issue.

SE: Let’s start with EUV. There is still an urgent need for EUV, right?

Van den hove: EUV, we believe, is the highest priority. It’s a higher priority than 450mm. We are still pushing very hard to get the first introduction of EUV at the 10nm node.

SE: What is the status of EUV?

Van den hove: With EUV, the need is there. Of course, if it was ready, we would already be using it for 14nm. Right now, the foundries are setting their layout rules such that EUV can be inserted at 10nm.

SE: What about 450mm?

Van den hove: It is very hard to predict if it will happen or not. What is clear is that there is a considerable delay. It’s a result of the economic situation. And indeed, we also need some consensus on multiple layers to get the market going. It’s a tremendous burden on the equipment suppliers. They also need time to develop this.

SE: What about the high-mobility materials for finFETs. Can you quantify the challenges with these types of materials?

Van den hove: The introduction of high-k materials at the 45nm and 32nm nodes was a major change. Introducing these mobility materials will be of the same complexity as the high-k materials. At the same time, everything we do is in a silicon-based fab. So, we need to make those high-mobility materials compatible with silicon processes. That’s one of the challenges. We need to make sure we can develop the right contact technology on top of those III-V materials. Typically, in a III-V fab, they are using other materials like gold contacts. We cannot use that in silicon-based fabs. So we have to adapt it to make it silicon compatible.

SE: Following finFET technology, chipmakers appear to be heading toward the development of gate-all-around FETs. Is that the case?

Van den hove: The scaling of the classical finFET will go down to 5nm or 7nm. And then, to go beyond that, you need better electrostatic control. So you need a gate-all-around. It seems to be the next step. And there are several ways to realize that. It can be done in horizontal fashion. It can also be in a vertical fashion. That may be the next step. In that case, you have a similarity with the NAND roadmap, which is moving vertically to 3D. We believe that may eventually happen in logic too.

SE: Can you briefly describe a gate-all-around structure?

Van den hove: In a planar FET, you control the charge in the channel in one direction. With the finFET or tri-gate, you have a structure that wraps around the gate and fin. In tri-gate, you control the charge from three directions. With gate-all-around, you wrap around the gate, so that you have full control over the charge of the channels.

SE: When do you see gate-all-around or a vertical nanowire structure appearing?

Van den hove: There will be a gradual evolution in terms of going from tri-gate to gate-all-around. But vertical nanowire is beyond a 5nm technology.

SE: What are the challenges with gate-all-around?

Van den hove: It is so radically different than what we are doing today. It’s a matter of more complex processing. It’s a matter of process control and delicate process optimization. From a vertical standpoint, it’s a completely new way of thinking. You have new processes that will be required. You may have nano-pillars. In the nano-pillars, you might have germanium and III-V. You can’t grow those nano-pillars epitaxially.

SE: Is Imec also looking at a monolithic 3D integration?

Van den hove: Absolutely. It’s a complex process. Once you make vertical transistors, you stack them on top of each other. We think it’s around a 5nm type of technology.

SE: Imec is looking at several technologies in the so-called beyond CMOS area. Is that correct?

Van den hove: We are pursuing several of those technologies. These are 3nm and beyond. Beyond 5nm, let’s say 3nm technology, you have to think in a different way. So that’s where we believe that a tunnel FET will come in, maybe at 3nm. That will probably be a vertical structure.

SE: Any thoughts on quantum computing and devices based on that technology?

Van den hove: It’s more at the university level right now, but we are watching it.

SE: So in the short- and long-term there are more options than ever, right?

Van den hove: There are lots of options out there. It’s a matter of taking the right road. Imec’s role is to help the industry to assess many of those options and seeing what are the most likely ones. We have developed a model to help our partners. In this extremely complex world, that type of model is needed.


[…] Earlier this year, Semiconductor Engineering caught up with Imec’s Van den hove to get his reading on the state of the industry, including 450mm technology, EUV, next-generation transistors and other subjects. […]

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