tag: 5nm

CEO Outlook: It Gets Much Harder From Here
By Ed Sperling - 03 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

Chiplet Momentum Builds, Despite Tradeoffs
By Brian Bailey - 13 May, 2019 - Comments: 0

Chip design is a series of tradeoffs. Some are technical, others are related to cost, competitive features or legal restrictions. But with the nascent 'chiplet' market, many of the established balance points are significantly altered, depending on market segments and ecosystem readiness. Chiplets provide an alternative mechanism for integrating intellectual property (IP) blocks into a semico... » read more

The Growing Uncertainty Of Sign-Off At 7/5nm
By Ann Mutschler - 09 May, 2019 - Comments: 3

Having enough confidence in designs to sign off prior to manufacturing is becoming far more difficult at 7/5nm. It is taking longer due to increasing transistor density, thinner gate oxides, and many more power-related operations that can disrupt signal integrity and impact reliability.  For many years, designers have performed design rule checks as part of physical verification of the desi... » read more

Making AI More Dependable
By Ed Sperling - 07 May, 2019 - Comments: 0

Ira Leventhal, vice president of Advantest’s new concept product initiative, looks at why AI has taken so long to get going, what role it will play in improving the reliability of all chips, and how to use AI to improve the reliability of AI chips themselves. » read more

Automotive System Design
By Ed Sperling - 06 May, 2019 - Comments: 0

Burkhard Huhnke, vice president of automotive at Synopsys, looks at how to build and update chips in increasingly sophisticated vehicles, where the problem spots are, and what comes next. » read more

IP Requires System Context At 6/5/3nm
By Ann Mutschler - 01 May, 2019 - Comments: 0

Driven by each successive generation of semiconductor manufacturing technology, complexity has reached dizzying levels. Every part of the design, verification and manufacturing is more complicated and intense the more transistors are able to be packed onto a die. For these reasons, the entire system must be taken into consideration as a whole – not just as individual building blocks as could ... » read more

Focus Shifting From 2.5D To Fan-Outs For Lower Cost
By Ed Sperling - 29 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 26 Apr, 2019 - Comments: 0

Fab tools and test Lam Research has developed a new self-maintaining or self-cleaning chamber for its etch tools. With the technology, Lam announced a new industry benchmark has been set for productivity in etch processing using its self-maintaining equipment. Etch process modules are typically cleaned weekly or monthly. Recently, Lam and a chipmaker reached the milestone of going 365 days... » read more

IC Design: Preparing For The Next Node
By Mentor, a Siemens Business - 25 Apr, 2019 - Comments: 0

The challenges of preparing for the next process node require constant preparation by the foundries, the EDA industry, and the design companies. Learn how Mentor works to prepare the Calibre nmPlatform for each “next node,” and ensure that its customers have the tools and performance they need to succeed. To read more, click here. » read more

Controlling IC Manufacturing Processes For Yield
By Ed Sperling - 24 Apr, 2019 - Comments: 0

Equipment and tools vendors are starting to focus on data as a means of improving yield, adding more sensors and analysis capabilities into the manufacturing flow to circumvent problems in real time. How much this will impact the cost of developing complex chips at leading-edge nodes, and in 2.5D and 3D-IC packages, remains to be seen. But the race to both generate data during manufacturing ... » read more

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